Wednesday, July 10, 2024

CHIPS R&D Office offer $1.6 Billion for Advanced Packaging

The CHIPS Research and Development Office has unveiled plans for a major funding initiative aimed at revolutionizing semiconductor advanced packaging in the United States. With up to $1.6 billion in cooperative agreements and other transaction agreements, this program seeks to establish domestic capacity for cutting-edge packaging technologies crucial for next-generation computing, AI, and low-power electronics.

This funding is part of the broader CHIPS and Science Act, which allocated $39 billion for semiconductor manufacturing incentives and $11 billion for R&D. The National Advanced Packaging Manufacturing Program (NAPMP) is a key component of this R&D effort, focusing on developing advanced packaging technologies to maintain U.S. leadership in the semiconductor industry.

The announcement outlines five primary R&D areas, with a strong emphasis on photonics, chiplets, and advanced packaging technologies:

1. Equipment, Tools, Processes, and Process Integration

2. Power Delivery and Thermal Management

3. Connector Technology, Including Photonics and Radio Frequency (RF)

4. Chiplets Ecosystem

5. Co-design/Electronic Design Automation (EDA)

In the realm of photonics, the program aims to develop low-loss optical connections between packaged sub-assemblies, enabling high-speed, low-latency data transfer. This technology is crucial for meeting the increasing bandwidth demands of advanced computing systems.

Chiplets are a central focus of the initiative, with an entire R&D category dedicated to developing a comprehensive chiplet ecosystem. This approach aims to enable the creation of application-specific integrated packages that surpass the capabilities of traditional monolithic ASICs, potentially revolutionizing semiconductor design and manufacturing.

Advanced packaging serves as the foundation for all R&D areas, with a focus on developing end-to-end packaging flows suitable for industry adoption. The program emphasizes heterogeneous integration and the dual goals of scaling down package features while scaling out to accommodate more chips per package.

“The National Advanced Packaging Manufacturing Program will enable a packaging sector within the United States that outpaces the world through innovation driven by robust R&D,” said Under Secretary of Commerce for Standards and Technology and National Institute of Standards and Technology (NIST) Director Laurie E. Locascio. “Within a decade, through R&D funded by CHIPS for America, we will create a domestic packaging industry where advanced node chips manufactured in the U.S. and abroad can be packaged within the United States and where innovative designs and architectures are enabled through leading-edge packaging capabilities.

The CHIPS R&D Office anticipates awarding multiple grants of up to $150 million each, with project durations of up to 5 years. The program strongly encourages collaboration between industry, academia, and non-profit organizations to foster a robust ecosystem for advanced packaging innovation.

Key Points:

• Total funding of up to $1.6 billion available for advanced packaging R&D

• Individual awards of up to $150 million for projects lasting up to 5 years

• Focus on five R&D areas, including photonics, chiplets, and advanced packaging

• Aim to establish domestic capacity for cutting-edge packaging technologies

• Part of the broader CHIPS and Science Act's $11 billion R&D initiative

• Emphasis on industry-academia collaboration to foster innovation ecosystem

• Prototype development opportunities included to demonstrate new packaging flows

This funding initiative represents a significant step in the U.S. government's efforts to reinvigorate domestic semiconductor research and manufacturing. By focusing on advanced packaging technologies, the program aims to position the United States at the forefront of the next wave of semiconductor innovation, crucial for maintaining technological leadership in an increasingly competitive global landscape.

https://www.nist.gov/news-events/news/2024/07/biden-harris-administration-invest-16-billion-establish-and-accelerate

https://www.nist.gov/system/files/documents/noindex/2024/07/09/CHIPS%20NAPMP%20NOI_07092024.pdf

Applied Materials unveils Advanced Chip Wiring and Stacking

Applied Materials introduced groundbreaking materials engineering innovations designed to enhance the performance-per-watt of computer systems. These innovations enable copper wiring to scale to the 2nm logic node and below, addressing the increasing demand for energy-efficient computing in the AI era. 

The industry faces significant challenges as it scales to 2nm and below. Current logic chips, which contain billions of transistors connected by miles of microscopic copper wiring, rely on a combination of low-k dielectrics and copper to deliver performance and power-efficiency improvements. However, thinner dielectric materials at these scales make chips mechanically weaker, and narrower copper wires increase electrical resistance, potentially reducing performance and increasing power consumption. Applied’s new enhancements to its Black Diamond™ material address these issues by reducing the minimum k-value and increasing mechanical strength, essential for 3D logic and memory stacking.

Additionally, Applied Materials introduced its latest IMS (Integrated Materials Solution), combining six technologies in one high-vacuum system. This system includes a binary metal combination of ruthenium and cobalt (RuCo), which reduces the thickness of the liner and improves surface properties for void-free copper reflow, ultimately reducing electrical line resistance by up to 25%. This innovation, the Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD, is being adopted by leading logic chipmakers and is set to enhance chip performance and power consumption significantly.


Key Points:

Materials Innovations: Applied Materials introduces enhancements to Black Diamond™ and a new IMS™ for advanced chip wiring and stacking.

Enhanced Performance: Innovations enable copper wiring to scale to 2nm, reducing electrical resistance and improving power efficiency.

Industry Adoption: Leading logic and DRAM chipmakers adopt Applied’s latest technologies, underscoring the company’s leadership in chip wiring processes.


Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials, highlighted the importance of chip wiring and stacking in improving performance and power consumption. The new integrated materials solution from Applied allows for low-resistance copper wiring at emerging angstrom nodes, while a new low-k dielectric material reduces capacitance and strengthens chips for advanced 3D stacking.

“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”


https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy

SEMI: Global semiconductor equipment sales to hit record $109B in 2024

Global sales of semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecasted to reach an unprecedented $109 billion in 2024, marking a 3.4% year-on-year growth, according to SEMI’s Mid-Year Total Semiconductor Equipment Forecast unveiled at SEMICON West 2024. This growth trajectory is expected to continue into 2025, with sales predicted to soar to $128 billion, driven by robust demand in both front-end and back-end segments.



The wafer fab equipment segment, encompassing wafer processing, fab facilities, and mask/reticle equipment, is set to grow by 2.8% to $98 billion in 2024, up from $96 billion last year. This revision from the previous $93 billion forecast is fueled by significant investments in China and rising demand for DRAM and high-bandwidth memory (HBM) due to AI computing. By 2025, wafer fab equipment sales are projected to increase by 14.7%, reaching $113 billion, propelled by advanced logic and memory applications.


After two years of contraction, the back-end equipment segment is expected to recover in the latter half of 2024. Sales of semiconductor test equipment are anticipated to rise by 7.4% to $6.7 billion, while assembly and packaging equipment sales are predicted to grow by 10.0% to $4.4 billion. This growth is expected to accelerate in 2025, with test equipment sales surging by 30.3% and assembly and packaging sales increasing by 34.9%. This rebound is supported by the growing complexity of semiconductor devices for high-performance computing and a recovery in demand across automotive, industrial, and consumer electronics markets.


Key Findings:

Wafer Fab Equipment: Expected to grow by 2.8% to $98 billion in 2024, reaching $113 billion by 2025.

Back-End Equipment: Projected recovery with a 7.4% increase in test equipment sales and a 10.0% rise in assembly and packaging equipment sales in 2024.

Regional Spending: China to lead equipment spending, projected to exceed $35 billion in 2024, despite expected contractions in other regions in 2024 with rebounds in 2025.


https://www.semi.org/en/semi-press-releases/global-total-semiconductor-equipment-sales-forecast-to-reach-record

Sparkle activates PoP at Rome’s Largest Data Centre Campus

Sparkle, Italy’s premier international service provider, and Aruba S.p.A, the country’s leading provider of cloud and data services, have announced the activation of a new Sparkle Point of Presence (PoP) at Aruba’s Hyper Cloud Data Centre in Rome. This new PoP, set to be inaugurated soon, strengthens Rome’s position as a global connectivity hub between Europe, Africa, the Middle East, and Asia, facilitated by Sparkle’s new BlueMed cable. The BlueMed cable is part of the Blue & Raman Submarine Cable Systems project, which, in collaboration with Google and other operators, aims to establish robust digital infrastructure linking various regions, including an extension to India under the IMEC initiative.


The BlueMed cable, designed with an open cable system and landing station architecture, offers unparalleled openness and interconnectivity, boasting a capacity of over 25 Terabits per second (Tbps) per pair across its four fibre pairs. This ensures high-speed, high-performance international connections from Rome to Sparkle’s global destinations. Sparkle’s new PoP at Aruba’s Hyper Cloud Data Centre, located in the Tecnopolo Tiburtino district, adds to Rome’s existing PoPs, enhancing the metropolitan ring’s redundancy and integration with Sparkle’s Tier-1 global IP network “Seabone.” This facility will provide various IP and data services, including DDoS Protection and Virtual NAP, benefitting network operators, ISPs, OTTs, and content providers.


Key Points:

New PoP Activation: Sparkle activates a new PoP at Aruba’s Hyper Cloud Data Centre in Rome.

BlueMed Cable: Enhances connectivity between Europe, Africa, the Middle East, and Asia, part of the Blue & Raman Submarine Cable Systems project.

High Performance: BlueMed cable offers over 25 Tbps per pair, supporting high-speed international connections.

Data Centre: Aruba’s Hyper Cloud Data Centre spans 74,000 m² with advanced infrastructure and renewable energy use.

Enhanced Services: PoP provides IP and data services, including DDoS Protection and Virtual NAP, via Sparkle’s Tier-1 global IP network.

AMD to acquire Silo AI for $665 Million, expanding AI capabilities

AMD agreed to acquire Silo AI, Europe’s largest private AI lab, for approximately $665 million in cash. This acquisition is a strategic move by AMD to enhance its end-to-end AI solutions based on open standards and to strengthen its partnership within the global AI ecosystem. Silo AI’s team, comprising world-class AI scientists and engineers, is known for developing customized AI models and platforms for leading enterprises across various markets, including cloud, embedded, and endpoint computing.

Peter Sarlin, CEO and co-founder of Silo AI, will continue to lead the Silo AI team under the AMD Artificial Intelligence Group, reporting to AMD senior vice president Vamsi Boppana. The acquisition, which is expected to close in the second half of 2024, will integrate Silo AI’s expertise into AMD’s existing AI initiatives. 

Based in Helsinki, Finland, Silo AI operates across Europe and North America, providing AI-driven solutions to customers like Allianz, Philips, Rolls-Royce, and Unilever. The company also develops open-source multilingual LLMs, such as Poro and Viking, on AMD platforms and offers its SiloGen model platform.

Key Points:

  • Acquisition Details: AMD to acquire Silo AI for $665 million in cash, expected to close in H2 2024.
  • Leadership: Silo AI CEO Peter Sarlin to lead the team within AMD Artificial Intelligence Group.
  • Silo AI Capabilities: Specializes in end-to-end AI solutions, serving customers like Allianz and Rolls-Royce, and develops open-source LLMs on AMD platforms.
  • Strategic Expansion: This acquisition aligns with AMD’s strategy to deliver open-standard AI solutions and follows recent investments in AI companies, including Mipsology and Nod.ai.

Norway's Sodvin replaces GPON with Ciena’s XGS-PON



Sodvin AS, a provider of telecommunications and energy solutions, is leveraging Ciena’s fiber broadband platform to improve the capacity and reach of its residential broadband services throughout Tr√łndelag county, Norway.


Utilizing its existing power infrastructure, Sodvin is deploying fiber-optic networks to extend broadband access to residents and businesses in the region. Ciena’s XGS-PON solution replaces previously deployed GPON technology, enabling the delivery of services such as internet and multicast television.



Sodvin’s new residential broadband network incorporates key components of Ciena’s PON solution, including 5164 Routers, XGS-PON uOLTs (micro optical line terminals), and 3801 ONUs (optical network units). Ciena’s uOLT pluggables allow Sodvin to expand deployment rapidly, easily, and sustainably, adding capacity in granular increments to match customer demand. XGS-PON can deliver symmetrical speeds of up to 10 Gb/s both downstream and upstream.


Virginie Hollebecque, Vice President of Europe, Middle East, and Africa at Ciena, stated, “Sodvin’s choice of Ciena’s broadband solution shows their commitment to staying at the forefront of technology, enabling them to deliver higher-speed services with unmatched flexibility and scalability to unlock new possibilities for their customers while reducing environmental impacts. We are delighted to count Sodvin as a customer, who supports the transition to a greener future through the use of sustainable technology.”


Infrastructure Upgrade: Sodvin upgrades to Ciena’s XGS-PON solution, replacing GPON technology.

Enhanced Services: New network supports symmetrical speeds of up to 10 Gb/s for internet and multicast television.