Sunday, June 9, 2024

Ultra Accelerator Link group aims for open interconnect standard

AMD, Broadcom, Cisco, Google, Hewlett Packard Enterprise (HPE), Intel, Meta and Microsoft agreed to develop an open industry standard for interconnecting AI accelerators.

The Ultra Accelerator Link (UALink) group will develop a specification to define a high-speed, low-latency interconnect for scale-up communications between accelerators and switches in AI computing pods.

The 1.0 specification will enable the connection of up to 1,024 accelerators within an AI computing pod and allow for direct loads and stores between the memory attached to accelerators, such as GPUs, in the pod. The UALink Promoter Group has formed the UALink Consortium and expects it to be incorporated in Q3 of 2024. The 1.0 specification is expected to be available in Q3 of 2024 and made available to companies that join the Ultra Accelerator Link (UALink) Consortium.

Ultra Accelerator Link Overview

  • The group plans to launch the organization and release the 1.0 spec for members in 3Q24
  • An update to increase the bandwidth will be released in 4Q24
  • The interconnect is for GPU-to-GPU communication
  • Direct load, store, and atomic operations between Al Accelerators (i.e. GPUs)
  • Low latency, high bandwidth fabric for 100's of accelerators
  • The initial UALink spec taps into the experience of the Promoters developing and deploying a broad range of accelerators and leverages the proven Infinity Fabric protocol

“The work being done by the companies in UALink to create an open, high performance and scalable accelerator fabric is critical for the future of AI. Together, we bring extensive experience in creating large scale AI and high-performance computing solutions that are based on open-standards, efficiency and robust ecosystem support. AMD is committed to contributing our expertise, technologies and capabilities to the group as well as other open industry efforts to advance all aspects of AI technology and solidify an open AI ecosystem.” – Forrest Norrod, executive vice president and general manager, Data Center Solutions Group, AMD

"Broadcom is proud to be one of the founding members of the UALink Consortium, building upon our long-term commitment to increase large-scale AI technology implementation into data centers. It is critical to support an open ecosystem collaboration to enable scale-up networks with a variety of high-speed and low-latency solutions.” – Jas Tremblay, vice president and general manager of the Data Center Solutions Group, Broadcom

“Ultra-high performance interconnects are becoming increasingly important as AI workloads continue to grow in size and scope. Together, we are committed to developing the UALink which will be a scalable and open solution available to help overcome some of the challenges with building AI supercomputers.” – Martin Lund, Executive Vice President, Common Hardware Group, Cisco

“Open standards are important to HPE as we innovate in supercomputing and increase access to systems. As a founding member of the UALink industry consortium, we look forward to contributing our expertise in high performance networking and systems, and collaborating to develop a new open standard for accelerator interconnects for the next generation of supercomputing.” – Trish Damkroger, senior vice president and general manager, HPC & AI Infrastructure Solutions, HPE

“UALink is an important milestone for the advancement of Artificial Intelligence computing. Intel is proud to co-lead this new technology and bring our expertise in creating an open, dynamic AI ecosystem. As a founding member of this new consortium, we look forward to a new wave of industry innovation and customer value delivered though the UALink standard. This initiative extends Intel’s commitment to AI connectivity innovation that includes leadership roles in the Ultra Ethernet Consortium and other standards bodies.” – Sachin Katti, SVP & GM, Network and Edge Group, Intel Corporation

“In a very short period of time, the technology industry has embraced challenges that AI and HPC have uncovered. Interconnecting accelerators like GPUs requires a holistic perspective when seeking to improve efficiencies and performance. At UEC, we believe that UALink’s scale-up approach to solving pod cluster issues complements our own scale-out protocol, and we are looking forward to collaborating together on creating an open, ecosystem-friendly, industry-wide solution that addresses both kinds of needs in the future.” – J Metz, Ph.D., Chair, Ultra Ethernet Consortium


Alphawave Semi collaborates with Arm on compute chiplets

Alphawave Semi is working with Arm to develop an advanced compute chiplet based on Arm Neoverse Compute Subsystems (CSS) for systems used in artificial intelligence/machine learning (AI/ML), high-performance computing (HPC), data centers, and 5G/6G networking infrastructure. This development follows Alphawave Semi's entry into the Arm Total Design ecosystem last year, which focuses on creating custom silicon solutions using Arm Neoverse CSS.

The chiplet-based custom silicon design platform from Alphawave Semi incorporates IO extension chiplets, memory chiplets, compute chiplets, and their ultra-high-speed connectivity IP and advanced packaging capabilities. The new compute chiplet features an Arm Neoverse N3 CPU core cluster and the Arm Coherent Mesh Network (CMN) for efficient, scalable performance. This technology, available on industry-leading process nodes, helps customers accelerate the development and reduce the time-to-market of new custom system-on-chip (SoC) technologies, supporting high-performance digital infrastructure deployment.

Alphawave Semi, in collaboration with Arm, leverages advanced packaging techniques and a portfolio of connectivity technologies, including PCIe Gen 6.0 and 7.0, Universal Chiplet Express (UCIe), 112/224G Ethernet, and HBM subsystems. This integration ensures robust performance and flexibility for Arm-based compute chiplets, addressing the needs of next-generation HPC, data center, AI/ML, and 5G/6G infrastructure while accelerating customer time-to-market.

Key Points:

  • Alphawave Semi and Arm have partnered to develop an advanced compute chiplet.
  • The chiplet is based on Arm Neoverse Compute Subsystems (CSS).
  • Applications include AI/ML, HPC, data centers, and 5G/6G networking infrastructure.
  • The chiplet platform includes IO extension, memory, and compute chiplets, with high-speed connectivity and advanced packaging.
  • Features Arm Neoverse N3 CPU core cluster and Arm Coherent Mesh Network (CMN).
  • Supports faster development and reduced time-to-market for custom SoC technologies.
  • Incorporates advanced connectivity technologies like PCIe Gen 6.0/7.0, UCIe, 112/224G Ethernet, and HBM subsystems.


Rapidus and IBM target 2nm chiplet packaging technology

Rapidus, headquartered in Tokyo, and IBM  announced a partnership focused on 2nm chiplet packaging technology. Rapidus will leverage IBM's advanced semiconductor packaging technology. This partnership is part of a broader international collaboration under the framework of the New Energy and Industrial Technology Development Organization (NEDO).

As part of this partnership, Rapidus engineers will work alongside IBM at its North American packaging research and development facility. IBM, with its extensive experience in high-performance semiconductor packaging and collaborations with Japanese semiconductor manufacturers, will provide the expertise and support needed for Rapidus to expedite the development of advanced chiplet packaging technology. Rapidus aims to solidify Japan's role in the semiconductor supply chain through this international collaboration.

Both Rapidus President Atsuyoshi Koike and IBM Senior Vice President and Research Director DarĂ­o Gil expressed their enthusiasm for this partnership. Koike emphasized the importance of this collaboration in enhancing Japan's semiconductor packaging capabilities, while Gil highlighted IBM's commitment to advancing chiplet technology and supporting new use cases and semiconductor talent development through this collaboration.

Key Points:

  • Rapidus and IBM have partnered to develop 2nm chiplet packaging technology.
  • The collaboration is part of NEDO's international framework for semiconductor technology development.
  • Rapidus engineers will work at IBM's North American R&D facility.
  • IBM brings extensive experience in high-performance semiconductor packaging.
  • The partnership aims to enhance Japan's role in the global semiconductor supply chain.


Joint ASML-imec Lab to accelerate High NA EUV for chip foundries

ASML and imec (Interuniversity Microelectronics Centre), a renowned research and development organization based in Leuven, Belgium, inaugurated a new High NA EUV Lithography Lab in Veldhoven, the Netherlands. 

The new facility is equipped with a prototype High NA EUV scanner (TWINSCAN EXE:5000) and surrounding processing and metrology tools.

The opening of the joint ASML-imec High NA EUV Lab marks a significant milestone in preparing High Numerical Aperture (NA) Extreme Ultraviolet (EUV) technology for high-volume manufacturing, projected for the 2025-2026 timeframe. This facility provides leading-edge logic and memory chip manufacturers access to a High NA EUV prototype scanner and essential tools, aiding them in de-risking the technology and developing private use cases before the scanners are operational in their production fabs. Additionally, the broader ecosystem of material and equipment suppliers, as well as participants in imec’s High NA patterning program, will also have access.

The readiness of the 0.55 NA EUV scanner and supporting infrastructure followed extensive preparations starting in 2018. ASML and ZEISS developed specific solutions for the High NA EUV scanner, addressing challenges such as the source, optics, lens anamorphicity, stitching, reduced depth of focus, edge placement errors, and overlay accuracy. Concurrently, imec and its extended supplier network prepared the patterning ecosystem, developing advanced materials, photomasks, metrology and inspection techniques, imaging strategies, optical proximity correction, and integrated patterning and etch techniques. These efforts culminated in the first successful exposures of 10 nm dense lines printed on metal oxide resists using the prototype scanner.

Key Points:

  • ASML and imec open High NA EUV Lab to prepare for high-volume manufacturing.
  • High NA EUV anticipated for production use in 2025-2026.
  • Lab provides access to prototype scanner and tools for chip manufacturers.
  • Broader ecosystem of material and equipment suppliers also gain access.
  • Preparations since 2018 involved ASML, ZEISS, and imec's extended network.
  • First successful exposures of 10 nm dense lines achieved with prototype scanner.


Italy's Fastweb sells its stake in FiberCop to KKR

Fastweb, which is the Italian subsidiary of Swisscom, agreed to sell its full 4.5% stake in FiberCop to KKR, the U.S.-based investment firm. The deal was valued at EUR 438.7 million, a value in line with the pro rata price paid by KKR to TIM for its stake. The transaction remains subject to the completion of the NetCo transazioni by KKR, closing is expected in Q3 2024.

Fastweb has been a shareholder in FiberCop – a company established by the Italian telecommunications company TIM, the American investment firm KKR to accelerate the development of fibre infrastructures in Italy – since its inception in 2021. The transaction has no effect on the wholesale agreement between Fastweb and FiberCop.

Fastweb said it remains fully committed to its mission of driving innovation and connectivity in the country through investments in key telecommunications infrastructures. Fastweb will therefore keep making relevant investments to increase the coverage of its proprietary, end-to-end controlled fiber network and will continue to be a key provider of wholesale services to third parties, ensuring the availability of robust and competitive offerings in the market.

The transaction remains subject to the completion of the NetCo transition by KKR, closing of the transaction is expected in Q3 2024.

  • In May 2024, the European Commission has approved unconditionally the acquisition by Kohlberg Kravis Roberts & Co. (KKR), a U.S.-based investment group, of NetCo., which comprises the primary and backbone fixed-line network business of Telecom Italia S.p.A. (‘TIM’) as well as FiberCop S.p.A (‘FiberCop’). FiberCop is a joint venture between TIM and KKR comprising TIM’s secondary fixed-line network. The deal, which was announced in November 2023, is valued at EUR 22 billion.


Indonesia's Telin builds Cable Landing Station for Bifrost cable

Telin hosted a groundbreaking ceremony for the Cable Landing Station (CLS) near Pantai Mutiara, a critical component of the Bifrost Cable System. 

The ambitious Bifrost cable will connect Singapore and North America through Indonesia, enhancing connectivity across the Java Sea and the Celebes Sea. The construction of the CLS marks a significant milestone in the project, which has been under development since March 2021, in collaboration with Keppel, Meta, and Google.

The Bifrost Cable System aims to address the increasing connectivity needs of Southeast Asia, offering seamless direct connectivity to North America, low latency, and network diversity. The project is poised to significantly bolster Indonesia’s international connectivity and support the region's digital transformation and economic growth.

Bifrost highlights

  • CLS Location: Near Pantai Mutiara, Indonesia.
  • Partners: Telin, Keppel, Meta, and Google.
  • Route: Connects Singapore, Indonesia, and North America via the Java and Celebes Seas.
  • Project Start: March 2021.
  • Strategic Gateways: Manado as the second international gateway after Batam.
  • System Length: Approximately 16,000 kilometers.
  • Landing Points: Guam, Indonesia, California, and Singapore.
  • Benefits: Enhanced connectivity, low latency, network diversity, and capacity resiliency for businesses and consumers.


Deep Blue One links French Guiana, Suriname, Guyana, T&T

Digicel Group announced the activation of its subsea fibre cable, Deep Blue One, linking the Caribbean and South America with landings in French Guiana, Suriname, Guyana and Trinidad & Tobago.

Marcelo Cataldo, Digicel Group’s Chief Executive Officer said, “Subsea fibre has long been the backbone of global connectivity, and Deep Blue One is set to serve as a catalyst for the next wave of economic development in the region. At Digicel, our focus has always been on keeping our customers connected to the people and things that matter most; driving economic development in the countries we serve is a key part of that. This is an exciting milestone for us, and we are committed to unlocking new opportunities for growth and innovation across the region.”

  • In 2021, Orange announced a financial investment to extend Digicel’s forthcoming Deep Blue One submarine network from Trinidad to French Guiana. The 2,000 km cable installation for Deep Blue One has five branching units, plus the capability to provide connectivity for offshore rigs, with anywhere from two to eight fibre pairs in each segment, offering a minimum of 12 Tbps capacity per fibre pair. The French Guiana leg to Trinidad is 1,600 km long.  In addition, Orange will act as landing party in Cayenne for the French Guiana branch and will operate the Cable landing station on behalf of Digicel while its subsidiary Orange Marine, will be in charge of laying the cable. Orange notes that Deep Blue One will complement its existing, fully-owned 1746 km long “Kanawa” cable, which was commissioned early 2019 as well as Orange’s existing networks based on Americas-2, ECFS, CBUS. Digicel noted that this extension of Deep Blue One will complement its existing Southern Caribbean Fiber network, which has approximately 3,000 km of submarine cable connecting 20 islands in the Eastern Caribbean.