Cavium Networks unveiled its next generation NITROX DPI II family of L7 content processors offering deep packet inspection across millions of definable rules at 40 Gbps.
The NITROX DPI II is a "bump-in--the-wire" single chip deep packet inspection processor designed for a range of enterprise, data center, and 3G/4G infrastructure equipment requiring fine grain content processing at wire speed. DPI processing enables advanced functions, such as protocol analysis, application recognition, intrusion prevention, anti-malware protection, URL Filtering, unified threat management, antivirus gateways, subscriber charging, application aware QOS and service level agreements, usage monitoring and preventing denial of service.
The new NITROX DPI II chip is enabled by Cavium's Hyper Finite Automata (HFA) engines and optimized TurboDPI software. It can be used in both inline and coprocessor modes. In coprocessor mode it connects over its in-built PCI Express interface to offload general purpose processors i.e. x86, MIPs or PowerPC based systems that lack such advanced hardware DPI engines.
The HFA engines in CN18XX family support highly complex rules and can process millions of rules without any performance impact. The NITROX DPI II family is fully software and rule syntax compatible with the DPI engines in Cavium's OCTEON II processor family and the NITROX DPI CN17XX family offering a wide variety of scalable and compatible system design options to customers.
"Our new NITROX DPI II product line further extends our reach into 'bump-in-the-wire' and coprocessor designs where power, space and real estate budget previously limited the ability to add complex deep packet inspection features," said Rajneesh Gaur, GM of the Coprocessors & Adapters Group, Cavium Networks. "Now OEMS building switches, routers and WAN appliances can more easily add DPI functionality."http://www.caviumnetworks.com
The NITROX DPI II is a "bump-in--the-wire" single chip deep packet inspection processor designed for a range of enterprise, data center, and 3G/4G infrastructure equipment requiring fine grain content processing at wire speed. DPI processing enables advanced functions, such as protocol analysis, application recognition, intrusion prevention, anti-malware protection, URL Filtering, unified threat management, antivirus gateways, subscriber charging, application aware QOS and service level agreements, usage monitoring and preventing denial of service.
The new NITROX DPI II chip is enabled by Cavium's Hyper Finite Automata (HFA) engines and optimized TurboDPI software. It can be used in both inline and coprocessor modes. In coprocessor mode it connects over its in-built PCI Express interface to offload general purpose processors i.e. x86, MIPs or PowerPC based systems that lack such advanced hardware DPI engines.
The HFA engines in CN18XX family support highly complex rules and can process millions of rules without any performance impact. The NITROX DPI II family is fully software and rule syntax compatible with the DPI engines in Cavium's OCTEON II processor family and the NITROX DPI CN17XX family offering a wide variety of scalable and compatible system design options to customers.
"Our new NITROX DPI II product line further extends our reach into 'bump-in-the-wire' and coprocessor designs where power, space and real estate budget previously limited the ability to add complex deep packet inspection features," said Rajneesh Gaur, GM of the Coprocessors & Adapters Group, Cavium Networks. "Now OEMS building switches, routers and WAN appliances can more easily add DPI functionality."http://www.caviumnetworks.com
a start-up based in Richardson, Texas, raised a further $10 million of Series B funding for its small cell radio products.
is introducing a Smart WLAN Connectivity Solution that selectively offloads mobile broadband traffic to Wi-Fi without any break in service. The user would not need to manually switch a device's data connection between Wi-Fi and cellular broadband. The solution also allows operators to use the existing services and functionality supported by its packet core network such as authentication, charging, policy control and traffic management for both mobile and Wi-Fi traffic in a unified way.
announced a low cost, low power integrated solution for femtocells and picocells. This latest Layer 1 firmware release runs on Octasic's previously announced OCT2224W SoC, based on its second generation asynchronous Opus2 DSP core, and is able to process up to 64 HSPA+ users on a single device. The solution will support indoor enterprise femtocells, indoor high capacity femtocells and picocells, outdoor picocells, and microcells.
Ericsson is scaling PON-based fiber access networks to 40 Gbps using Wavelength Division Multiplexing Passive Optical Network (WDM-PON) technology. The capability is being added to the EA 1100 platform, which is a result of a joint venture with LG-Ericsson.
is introducing an antenna integrated radio (AIR) solution supporting 3G and 4G and promising significant energy savings. The compact, multi-standard solution ensures highly efficient and smooth introduction of new technologies. A new standard or a new frequency band can easily be introduced by simply adding AIR and swapping the existing antenna. Field trials have already shown a reduction of integration and installation time of up to 30 percent compared to traditional site solutions. The field trial also demonstrated that the solution provides reduced power consumption of up to 42 percent, mainly due to reduced feeder loss and simplified cooling.
