Thursday, January 26, 2023

Intel delivers a weak financial report

Intel reported Q4 revenue of $14.0 billion, down 32 percent year-over-year (YoY) and down 28 percent YoY on a non-GAAP basis. Full-year revenue was $63.1 billion, down 20 percent YoY and down 16 percent YoY on a non-GAAP basis. Q4 earnings (loss) per share (EPS) was $(0.16); non-GAAP EPS was $0.10. Full-year EPS was $1.94; non-GAAP EPS was $1.84.

"Despite the economic and market headwinds, we continued to make good progress on our strategic transformation in Q4, including advancing our product roadmap and improving our operational structure and processes to drive efciencies while delivering at the low-end of our guided range. In 2023, we will continue to navigate the short-term challenges while striving to meet our long-term commitments, including delivering leadership products anchored on open and secure platforms, powered by at-scale manufacturing and supercharged by our incredible team," stated Pat Gelsinger, Intel CEO.

Quarterly revenue for the Client Computing Group (CCG) was down 36% compared to last year, while sales for Data Center and AI (DCAI) was down 33%.  The Network and Edge (NEX) group was down only 1%, while Mobileye grew 59% compared to a year earlier.  The Intel Foundry Services business recorded $319 million in sales for the quarter, up 30% compared to a year earlier.

Looking ahead to the current Q1 2023, Intel is forecasting a deeper loss of $(.80) per share for the quarter.

Intel cuts Switching and Pathfinder for RISC-V

As part of cost-cutting measures, Intel will discontinue development of its network switching product line. The Tofino switching silicon products were part of the acquisition of Barefoot Networks. 

 Prepared comments from CEO Pat Gelsinger for the Q4 investor call: 

"We enter 2023 with a view that much of the macro uncertainty of the last year is likely to persist, especially in the first half of the year. As such we are laser-focused on executing to our $3 billion in CY23 cost savings that we committed to on our Q3 earnings call. We are making tough decisions to right-size the organization, and we further sharpened our business focus within our BUs (business units) by rationalizing product roadmaps and investments. NEX continues to do well and is a core part of our strategic transformation, but we will end future investment on our network switching product line, while still fully supporting existing products and customers. Since my return, we have exited seven businesses, providing in excess of $1.5 billion in savings. We are also well underway to integrating AXG (Accelerated Computing Systems and Graphics) into CCG (Client Computing Group) and DCAI (Data Center and AI Group), respectively, to drive a more effective go-to-market capability, accelerating the scale of these businesses while further reducing costs."

Intel also posted notices regarding a discontinuation of its Pathfinder for RISC-V tool, which enables the exploration of RISC-V IP utilizing FPGA platforms. The software supported development on and testing of a wide range of opensource and commercial RISC-V processors in an FPGA environment.

Intel to acquire Barefoot Networks for programmable switching silicon

Intel agreed to acquire Barefoot Networks, a start-up developing programmable Ethernet switch silicon and software for use in the data center. Financial terms were not disclosed. Intel said the acquisition will support its focus on end-to-end cloud networking and infrastructure, enabling it to better compete in the Ethernet switching segment. Barefoot, which is based in San Jose, California, is shipping the second generation of its P4-programmable...

Barefoot's Tofino 2 chip delivers 12.8 Tbps switching for 32x400GE

Barefoot Networks is now sampling its Tofino 2 chip, the second generation of its P4-programmable Tofino Ethernet switch application-specific integrated circuit (ASIC) family. Tofino 2 doubles the performance of the first generation Tofino chip, now delivering 12.8 Tbps of packet processing capacity for hyperscale data centers, cloud, enterprise and service provider networks. The device leverages 7nm process technology and is designed for full P4-programmability. Tofino...

AT&T sees progress with open, disaggregated systems

AT&T is making significant progress with its open, disaggregated program. In a blog post, Mike Satterlee, vice president, Network Core Infrastructure Services, cites the following milestones:

  •  More than 52% of all production traffic are delivered over Next-Gen Core routers, which are based on the Broadcom Jericho2, Ramon chips and which use the Distributed Dis-Aggregated Chassis (DDC) design powered by DriveNets Network Cloud DNOS software. AT&T is exploring a path to scale the system to 500 Tbps and then to 900 Tps using next-gen chipset.
  • Next-Gen Edge Router – This platform provides enterprise services, Ethernet, Broadband, Mobility, and Internet Gateway using Broadcom, Cisco, and UfiSpace hardware. It is deployed it in AT&T production Internet peering network.
  • Cell Site Gateway Router – This supports up to 100Gbps Mobility transport to provide the bandwidth demands that come with 5G services. This solution uses hardware from UfiSpace, Broadcom Qumran-AX chips, coupled with the Vyatta NOS software from Ciena. This has been deployed in AT&T’s mobility network.
  • Ethernet Mux – This enables aggregation of 1 and 10 Gig access ports to 100 Gig transport.  This platform is based on Broadcom’s Qumran-MX chips and uses EdgeCore hardware with Ciena’s SAOS Network Operating System software. This is now live on the Metro Ethernet and fiber footprint.
  • Universal CPE – This broadband customer premise equipment today now provides high speed Dedicated Internet and Enterprise SD-WAN services. It uses Intel, Broadcom, Marvell and Silicom to put together a cost-effective and feature-rich device using Vyatta NOS software from Ciena. 
  • Open ROADM - Open ROADM provides the high speed and high-capacity optical transport supporting our fiber-based broadband and 5G backhaul. We have Open ROADM compliant components developed from Ciena, Cisco, Fujitsu, Infinera, and Nokia and have installed over 75+ nodes and turned up 100G and 400G wavelengths in our production network.

OCP and Jedec to standardize chiplet part descriptions

The Open Compute Project Foundation (OCP) and JEDEC Solid State Technology Association agreed to establish a framework for the transfer of technology captured in an OCP-approved specification to JEDEC for inclusion in one of its standards. This alliance brings together members from both the OCP and JEDEC communities to share efforts in developing and maintaining global standards needed to advance the electronics industry. 

Under this new alliance, the current effort will be to provide a mechanism to standardize Chiplet part descriptions leveraging OCP Chiplet Data Extensible Markup Language (CDXML) specification to become part of JEDEC JEP30: Part Model Guidelines for use with today’s EDA tools. With this updated JEDEC standard, expected to be published in 2023, Chiplet builders will be able to provide electronically a standardized Chiplet part description to their customers paving the way for automating System in Package (SiP) design and build using Chiplets. The description will include information needed by SiP builders such as Chiplet thermal properties, physical and mechanical requirements, behavior specifications, power and signal integrity properties, testing the Chiplet in package, and security parameters.

"One of the key efforts at the OCP is centered around the need for specialized computation for AI and ML workloads driving the need for specialized silicon. To deliver on the need for specialized silicon while enabling a rapid pace of innovation, we believe a new open Chiplet economy with a low barrier to entry is needed and will require collaboration and standardizations on multiple dimensions, ensuring that companies are able to interact in an open efficient and scalable manner. The OCP has been investing in being a catalyst for an open Chiplet economy for several years through its Open Domain Specific Architecture (ODSA) Project and are pleased to establish this alliance with JEDEC to allow work done in ODSA to become part of a global international standard that advances the industry," said Cliff Grossner, Ph.D., VP Market Intelligence & innovation at the Open Compute Project Foundation.

What next for data center interconnects in 2023?

Will public cloud spending come under budgetary scrutiny more than ever in 2023?  What about AI/ML workloads?

Here are 3 predictions for 2023 from Cyxtera's' *Holland Barry* .

-- *Check out other 2023 Predictions* --

See what other experts have to say on *NextGenInfra*

 -- *Amplify your MWC 2023 presence* --

Looking to record your video for our channel for our *MWC 2023 Showcase* in Barcelona?  We will be there! Book your session now. 

What's next for 5G in 2023?

Will 5G mmWave become a driving force for enterprise innovation? 

Here are 3 predictions for 2023 from Movandi's' *Maryam Rofougaran* .

-- *Check out other 2023 Predictions* --

See what other experts have to say on *NextGenInfra*

 -- *Amplify your MWC 2023 presence* --

Looking to record your video for our channel for our *MWC 2023 Showcase* in Barcelona?  We will be there! Book your session now. 

SENKO sues US Conec over connector IP

SENKO Advanced Components filed a lawsuit in the federal court of Delaware alleging US Conec, Ltd has infringed seven of its patents relating to the MDC and MMC connector and adapter products – VSFF products.

“SENKO has invested considerable time and resources in developing what we consider the industry’s broadest VSFF product portfolio, says Jim Hasegawa, Executive Vice President. “SENKO currently has over 70 issued VSFF related Patents covering this technology, and many additional claims are still pending. In view of our investment to create the VSFF portfolio, Senko believes it must take steps to protect its valuable intellectual property."