Ikanos Communications introduced IPTV-optimized, multi-mode VDSL2 chipsets for Central Office (CO), Remote Terminal (RT) and Customer Premises Equipment (CPE).
The company said its fifth generation chipsets are designed to provide the highest throughput and density, with the lowest power consumption per port. All chipsets comply with mandatory and optional features of the VDSL2 (ITU-T G.993.2) standard. Both CO and CPE chipsets also support VDSL1 (ITU-T G.993.1), ADSL (ITU-T G.992.1), ADSL2 (ITU-T G.992.3) and ADSL2+ (ITU-T G.992.5) and offer true plug-and-play multi-mode operation per port. The chipsets support all band plans that are defined in the standards for their respective profiles.
Significantly, Ikanos has enhanced its chipsets with integrated QoS capabilities at the PHY layer. An on-chip DSP engine provides seamless Dynamic Rate Repartitioning (DRR) for real-time, demand-driven reallocation of bandwidth between different services on the same line. This provides priority for voice or video packets across the line.
Ikanos is also adding enhanced impulse noise protection schemes for optimal IPTV delivery. The chips provide support of dual latency, dual interleaving over all network interfaces, and offer maximum interleaver and deinterleaver memory for highest impulse noise protection.
The full chipset consists of:
The four-chip architecture enables density of 48 ports, in small form-factor, power-constrained line cards.
http://www.ikanos.com
The company said its fifth generation chipsets are designed to provide the highest throughput and density, with the lowest power consumption per port. All chipsets comply with mandatory and optional features of the VDSL2 (ITU-T G.993.2) standard. Both CO and CPE chipsets also support VDSL1 (ITU-T G.993.1), ADSL (ITU-T G.992.1), ADSL2 (ITU-T G.992.3) and ADSL2+ (ITU-T G.992.5) and offer true plug-and-play multi-mode operation per port. The chipsets support all band plans that are defined in the standards for their respective profiles.
Significantly, Ikanos has enhanced its chipsets with integrated QoS capabilities at the PHY layer. An on-chip DSP engine provides seamless Dynamic Rate Repartitioning (DRR) for real-time, demand-driven reallocation of bandwidth between different services on the same line. This provides priority for voice or video packets across the line.
Ikanos is also adding enhanced impulse noise protection schemes for optimal IPTV delivery. The chips provide support of dual latency, dual interleaving over all network interfaces, and offer maximum interleaver and deinterleaver memory for highest impulse noise protection.
The full chipset consists of:
- The Fx100100-5 CO/RT chipset and the Fx100100S-5 CPE chipset, which support all VDSL2 profiles -- 8a, 8b, 8c, 8d, 12a, 12b, 17a and 30a --and are optimized for 30 MHz spectrum operation to offer 100/100 Mbps performance, and
- The Fx10050-5 CO/RT chipset and the Fx10050S-5 CPE chipset, which support VDSL2 profiles -- 8a, 8b, 8c, 8d, 12a, 12b and 17a -- and are optimized for 17.6 MHz spectrum utilization to offer 100/50 Mbps performance.
The four-chip architecture enables density of 48 ports, in small form-factor, power-constrained line cards.
http://www.ikanos.com