
Cadence Design Systems introduced its Janus Network-on-Chip (NoC) technology for managing data delivery between silicon components in complex SoCs and disaggregated multi-chip systems. The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.The Cadence Janus NoC leverages Cadence's trusted Tensilica RTL generation tools...