Keysight automates PCIe and UCIe chiplet design

Keysight Technologies introduced PCIe Designer, a new addition to its Advanced Design System (ADS) suite, designed to support simulation workflows for high-speed, high-frequency digital designs. This intelligent design environment is tailored for modeling and simulating the latest Peripheral Component Interconnect Express (PCIe) Gen5 and Gen6 systems. Additionally, Keysight has enhanced its electronic design automation (EDA) platform by upgrading the Chiplet PHY Designer tool to estimate chiplet die-to-die link margin performance and Voltage Transfer Function (VTF) compliance.

PCIe is a critical interface standard in the electronics industry, known for its high-speed data transfer, scalability, and adaptability. Its applications range from consumer electronics to high-performance computing and critical infrastructure systems. Keysight’s new PCIe Designer and enhanced Chiplet PHY Designer aim to simplify complex design processes and ensure compliance, thereby improving productivity and reducing time-to-market.

Key Features and Enhancements:

• PCIe Designer:
• Automates setup for multi-link, multi-lane, and multi-level (PAM4) PCIe systems.
• Simplifies simulation setup, reducing time-to-first-insight.
• Facilitates quick AMI model generation for system analysis.
• Supports NRZ and PAM4 modulations with wizard-driven AMI model generation for transmitters (Tx) and receivers (Rx).
• Streamlined, simulation-driven virtual compliance testing to ensure design quality and reduce design costs.
• Chiplet PHY Designer Enhancements:
• First simulation solution for Universal Chiplet Interconnect Express (UCIe) standards.
• Predicts die-to-die link margin, VTF for channel compliance, and forwarded clock capability.
• New design exploration and report generation features for accelerated signal integrity analysis and compliance verification.