MaxLinear employs Cadence for 400Gbps PAM4 chip using 16FF

MaxLinear used Cadence timing signoff tools to deliver its MxL935xx Telluride device, the first 400Gbps PAM4 system on chip (SoC) using 16FF process technology.

Cadence said its Quantus Extraction Solution and Tempus Timing Signoff Solution were key enablers of the on-time delivery of working silicon for MaxLinear.

MaxLinear's Telluride device can be used by system vendors to develop a 400Gbps optical interconnect module in a compact form factor for intra-datacenter applications with a transmission distance up to 2 kilometers.

“Managing heavily congested and high-speed SoC design throughout the design flow with high-target utilization to reduce costs at 16FF node is a challenging task,” said Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear. “We are able to deploy the full-flow Cadence digital and signoff tool set including their Quantus, Tempus, and Tempus ECO solutions for successful signoff and on-time tapeout. Using these signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.”