Avicena unveiled its new scalable LightBundle chiplet interconnect for extending ultra-high density die-to-die (D2D) connections up to 10m at multi-Tbps/mm shoreline bandwidth density and sub-pJ/bit energy efficiency.
The new chiplet interconnect, which is based on Avicena’s LightBundle platform, supports unprecedented shoreline density and energy efficiency for HPC and AI cluster architectures.
Currently, High Bandwidth Memory (HBM) modules must be located within a few millimeters of a Graphics Processing Unit (GPU), limiting accessible memory bandwidth and capacity based on GPU shoreline.
Avicena says its LightBundle chiplet interconnect extends HBM and other ultra-high performance D2D connections up to 10m while dissipating < 1pJ/bit for the optical interconnect and supporting multi-Tbps/mm beachfront density. This enables GPUs and other high-performance ICs to greatly increase their total IO bandwidth, accessing vastly more HBM and relieving inter-processor bottlenecks. The LightBundle chiplet is compatible with standard multichip packaging and supports a wide range of D2D interfaces including standard and advanced versions of UCIe and BOW. Avicena is working with selected partners on different implementations. Initial prototypes will be available in the second half of 2025.
“At Avicena, we are excited to announce our ultra-low power scalable chiplet interconnect based on our LightBundle platform,” says Bardia Pezeshki, Founder and CEO of Avicena. “The first D2D implementation will be an 8Tbps UCIe advanced interconnect with a total chiplet footprint of 4mm x 7mm, beachfront density of 2Tbps/mm and power consumption of < 12W.”
