Barefoot Networks is now sampling its Tofino 2 chip, the second generation of its P4-programmable Tofino Ethernet switch application-specific integrated circuit (ASIC) family.
Tofino 2 doubles the performance of the first generation Tofino chip, now delivering 12.8 Tbps of packet processing capacity for hyperscale data centers, cloud, enterprise and service provider networks. The device leverages 7nm process technology and is designed for full P4-programmability.
Tofino 2 highlights:
- World’s first 7nm switch ASIC
- Supports up 32x400GE on a single chip.
- Supports up to 256x10/25/50GE ports on a single chip.
- Fully P4-programmable, enabling various deployment options, from a standard top-of-rack switch to a service provider router, or even a feature-rich switch appliance.
- Support for unrivaled table sizes for routing, tunnels, and access control lists (ACLs).
- Support for Barefoot SPRINT™- Barefoot's enhanced version of the industry-standard In-band Network Telemetry (INT), providing fine-grained per-packet intelligent real-time visibility of network traffic.
- Leverages the growing industry-wide P4 Ecosystem supported by multiple switch and network interface controller (NIC) chips.
- Modular architecture enabling rapid integration of 112G SerDes and silicon photonics.
Customers cited in the Barefoot press release include Goldman Sachs, Cisco, Alibaba Infrastructure Services, Tencent, Baidu, JD Cloud, and Ucloud.
https://www.barefootnetworks.com/products/brief-tofino-2/