Rambus introduced a Quantum Safe Engine (QSE) for integration into hardware security elements in ASICs, SoCs and FPGAs.
The Rambus QSE IP core uses NIST-selected quantum-resistant algorithms to protect valuable data center and government hardware against attacks emerging in the post quantum computing era.
The Rambus QSE IP is available as a standalone cryptographic core or integrated in the Rambus Quantum Safe Root of Trust IP as a comprehensive hardware security solution. It supports the National Institute of Standards and Technology (NIST) draft standards for quantum-resistant algorithms (FIPS 203 ML-KEM and FIPS 204 ML-DSA), and provides SHA-3, SHAKE-128 and SHAKE-256 acceleration.
“From AI, to streaming video, to email, the applications we rely on daily depend on the integrity of data and must be guarded against the growing risk of attacks enabled by quantum computers,” said Neeraj Paliwal, general manager of Silicon IP at Rambus. “The Rambus Quantum Safe Engine is another important addition to our security IP portfolio helping customers transition to Quantum Safe Cryptography starting today.”
“Quantum computers will provide individuals and organizations the exponential speed-up and compute power needed to solve some of today’s most complex problems, including the ability to decrypt current data encryption algorithms,” said Heather West, PhD, research manager of Quantum Computing Research at IDC. “Implementing quantum-resistant cryptography now is key for organizations to protect their past, current and future data from quantum computing enabled attacks.”
https://www.rambus.com/security/quantum-safe-cryptography/qse-ip-86
