Samsung announces 12-Layer 3D-TSV chip packaging

Samsung Electronics announced the industry's first 12-layer 3D-TSV (Through Silicon Via) technology.

Samsung's new packaging technology vertically interconnects 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair. The thickness of the package (720㎛) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

Samsung says that by increasing the number of stacked layers from eight to 12, it will be able to mass produce 24-gigabyte (GB) High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC)," said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics. "As Moore's law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology."