Samsung Foundry looks to 3nm Gate-All-Around technology

The evolution of advanced foundry technologies will be crucial to enable the design and manufacture of innovative semiconductors for AI, cloud computing, autonomous vehicles, and smart home applications, said Dr. ES Jung, president and head of Foundry Business at Samsung Electronics, speaking at the 2018 IEEE* International Electron Devices Meeting (IEDM).

Dr. Jung introduced some of recent research and development in future silicon technology, including MRAM, a non-volatile memory solution embedded in conventional logic process, and 3nm Gate-All-Around (GAA) technology.

Samsung calculates that MRAM will be far more power efficient than conventional technologies, consuming only 0.5% of power compared to SRAM at 1,024Mb. MRAM also has smaller cell area, which allows design flexibility.

Samsung's unique GAA technology called Multi-Bridge-Channel FET (MBCFET) uses vertically stacked multiple nanosheet channels. With variable width of nanosheet, this technology provides not only optimal performance and power characteristics but also high design flexibility. Furthermore, MBCFET is fabricated using 90% or more of FinFET process with only a few revised masks, allowing easy migration.

Also with one of its newly published papers at 2018 IEDM, Samsung Electronics shared the development progress of 3nm, a successful demonstration of fully functioning high-density SRAM circuit. The development of Samsung's first process node applying MBCFET technology is on schedule.

https://www.samsungfoundry.com

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Samsung and eSilicon tape-out 14 nm network processor

Samsung Electronics announced a successful network processor tape-out based on its 14LPP (low-power plus) process technology that was implemented in collaboration with eSilicon and Rambus.

The network processor tape-out was based on Samsung's advanced foundry process and design infra for network applications, eSilicon's complex ASIC and 2.5D design capability with its IP solutions and a high-speed 28 Gbit/s SerDes solution from Rambus.

Samsung noted that its 14LPP process technology, based on 3D FinFET structure, has been proven for performance and manufacturability through mass production The next generation process for network application is 10LPP process, based on 10LPE (low-power early), for which production commenced last year, with mass production scheduled to begin by the end of 2017.

Samsung has also named its newly developed 2.5D turnkey solution, which serves to connect a logic chip and HBM2 memory via an interposer, as I-Cube (Interposer-Cube). The 14LPP network process chip is the first product to feature its I-Cube solution and HBM2 memory and is designed to support key network applications for high-speed signalling, and potentially further applications such as computing, server and AI in the future.

Commenting on the achievement, Patrick Soheili, VP of product management and corporate development at eSilicon, said, "eSilicon brings its FinFET ASIC and interposer design skills, along with 2.5D integration skills to the project… its HBM Gen2 PHY, custom flip-chip package design and custom memory designs also helped to optimise the power, performance and area for the project".

While Rambus' Luc Seraphin, SVP and GM, memory and interfaces division, noted, "Networking OEMs are looking for quality… IP suppliers that can bring 28 Gbit/s backplane SerDes in advanced FinFET process nodes to market… the success with Samsung and eSilicon is a testament that these leading solutions are attainable…".

http://www.samsung.com

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