Achieving scale-up and scale-out AI systems requires an advanced networking fabric. In his keynote. Intel CEO Pat Gelsinger said he expects Ultra Ethernet to meet this requirement.
Intel isintroducing an array of AI-optimized Ethernet solutions, including a network interface card, AI chiplets, as well as soft and hard IP through Intel Foundry. These Ultra Ethernet developments build on Intel’s work with integrating Xeon and Gaudi into AI systems. “We don’t need proprietary networking solutions for our AI systems,” said Gelsinger.
In addition, Intel announced new edge silicon across the Intel Core Ultra, Intel Core and Intel Atom processor and Intel Arc graphics processing unit (GPU) families of products, targeting key markets including retail, industrial manufacturing and healthcare. All new additions to Intel’s edge AI portfolio will be available this quarter and will be supported by the Intel Tiber Edge Platform this year.
Ultra Ethernet Consortium targets networking for AI and HPC
A new Ultra Ethernet Consortium (UEC) has been established with the goal of bringing together leading companies for industry-wide cooperation to build a complete Ethernet-based communication stack architecture for high-performance networking. UEC is
The aim is to capitalize on Ethernet's ubiquity and flexibility for handling a wide variety of workloads in Artificial Intelligence (AI) and High-Performance Computing (HPC).
Founding members of Ultra Ethernet Consortium, which is a Joint Development Foundation project hosted by The Linux Foundation , include AMD, Arista, Broadcom, Cisco, Eviden (an Atos Business), HPE, Intel, Meta and Microsoft.
The consortium will follow a systematic approach with modular, compatible, interoperable layers with tight integration to provide a holistic improvement for demanding workloads. The founding companies are seeding the consortium with highly valuable contributions in four working groups: Physical Layer, Link Layer, Transport Layer and Software Layer.
The technical goals for the consortium are to develop specifications, APIs, and source code to define:
- Protocols, electrical and optical signaling characteristics, application program interfaces and/or data structures for Ethernet communications.
- Link-level and end-to-end network transport protocols to extend or replace existing link and transport protocols.
- Link-level and end-to-end congestion, telemetry and signaling mechanisms; each of the foregoing suitable for artificial intelligence, machine learning and high-performance computing environments.
- Software, storage, management and security constructs to facilitate a variety of workloads and operating environments.
"This isn't about overhauling Ethernet," said Dr. J Metz, Chair of the Ultra Ethernet Consortium. "It's about tuning Ethernet to improve efficiency for workloads with specific performance requirements. We're looking at every layer - from the physical all the way through the software layers - to find the best way to improve efficiency and performance at scale."
