At this week's ECOC in Glasgow, Avicena is demonstrating its LightBundle multi-Tbps chip-to-chip interconnect technology.
Currently, high-bandwidth memory (HBM) modules must be co-packaged with GPUs because the GPU-memory electrical interconnect is limited to just a few millimeters in length. Conventional optical interconnects based on VCSELs or Silicon Photonics (SiPh) promise to extend the interconnect reach. However, they are challenged by the power, bandwidth density, latency, and cost requirements.
Avicena says its microLED-based LightBundle interconnects provide much lower power and latency, much higher bandwidth density, and can achieve very low costs.
The LightBundle interconnect architecture is based on arrays of GaN microLEDs that leverage the microLED display ecosystem and can be integrated directly onto high performance CMOS ICs. Each microLED array is connected via a multi-core fiber cable to a matching array of CMOS-compatible PDs.
“As generative AI continues to evolve, the role of high bandwidth-density, low-power and low latency interconnects between xPUs and HBM modules cannot be overstated”, says Chris Pfistner, VP Sales & Marketing of Avicena. “Avicena’s innovative LightBundle interconnects have the potential to fundamentally change the way processors connect to each other and to memory because their inherent parallelism is well-matched to the internal wide and slow bus architecture within ICs. With a roadmap to multi-terabit per second capacity and sub-pJ/bit efficiency these interconnects are poised to enable the next era of AI innovation, paving the way for even more capable models and a wide range of AI applications that will shape the future.”
“We have previously demonstrated microLEDs transmitting at > 10Gbps per lane and a test ASIC in a 130nm CMOS process running 32 lanes at less than 1pJ/bit,” says Bardia Pezeshki, founder and CEO of Avicena. “Now we are bringing up our first ASIC in a 16nm finFET process with over 300 lanes and an aggregate bandwidth of over 1Tbps bi-directional at 4Gbps per lane. The ASIC measures less than 12mm2 and contains the circuitry for the optical Tx and Rx arrays, as well as a high-speed parallel electrical interface and various DFT/DFM functions like BERT, loopbacks, and Open Eye Monitoring (OEM). All key ASIC functionality has been verified and we are currently working on yield improvements for manufacturing scalability.”
Avicena plans to advance its LightBundle platform to enable interconnects with high-bandwidth density of multi-Tbps per mm2 in advanced CMOS process nodes. The low power, high density, and low latency of LightBundle is well matched to chiplet interfaces like UCIe, OpenHBI, and BoW, and can also be used to enhance system architectures that are limited by the reach of existing compute interconnects like PCIe/CXL, and HBM/DDR/GDDR memory links.
https://avicena.tech
