OIF launched an enhanced SGMII project – a Physical & Link Layer (PLL) Working Group Electrical track project.
The enhanced SGMII (E-SGMII) specifications will be based on modernized current mode logic (CML) electrical specifications instead of legacy LVDS and provide an optional high-speed 1 GbE interface to supplement the management of modules. Specifically, it will define a 1 GbE (1.25 GBd) high-speed serial interface for modules based on a modernized, enhanced SGMII. E-SGMII will have applications both for next-generation modules and for existing form factors with sufficient pins available.
At the first Technical and MA&E Committees Meeting of 2023, OIF also celebrated its 25th anniversary and noted the completion of the Common Electrical I/O (CEI)-112G-VSR.
CEI-112G-VSR-PAM4 specifies a 112 Gb/s chip-to-module PAM4 electrical interface for use in the range 36 to 58 Gsym/s with up to 16 dB loss at the Nyquist frequency, including one connector. Hosts and modules compliant to CEI-112G-VSR-PAM4 from different manufacturers are interoperable.
“CEI-112G-VSR allows for an interoperable environment using optical pluggable modules critical to networking and challenging AI/ML connectivity,” said Dr. Karl Bois, OIF Technical Committee Vice Chair, NVIDIA Corporation. “The networking and data center ecosystems have a new powerful implementation recipe to increase throughput and capacity, especially when the network is part of the Compute infrastructure.”
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