Credo released its new 3.2Tbps BlueJay retimer chiplet for providing system-level connectivity with 64 lanes of 56Gbps PAM4 LR DSP connectivity.
BlueJay communicates with the MCM system-on-chip (SoC) core on the host side using an ultra-low-power Bunch of Wires (BoW) die-to-die interface. The wide-bus BoW interface is optimized for the TSMC CoWoS packaging technology designed for high-performance computing applications. On the line side, the chiplet has 64 lanes of low-power 56G PAM4 LR SerDes to deliver a robust, off-package interface for the MCM, which allows for easy integration in various system-level configurations.
“Integrating chiplets allows our customers to accelerate ASIC designs with increased performance to support advanced switching, storage, high-performance computing, AI, machine learning, and service provider applications. These data intensive applications place a wide range of architectural demands on next-generation ASICs,” said Michael Girvan Lampe, Vice President of Worldwide Sales at Credo.
"BlueJay is the second Credo 3.2Tbps retimer chiplet to enter production this year. All of Credo's silicon-proven chiplets, with 56G and 112G lane rates plus SerDes DSP IP, provide ASIC designers with diverse options to achieve their time-to-market and performance objectives,” Lampe continued.
Credo's unique SerDes technology allows the BlueJay chiplet to be manufactured in TSMC's 28nm process.
