Intel intros Tremont microarchitecture

Intel unveiled Tremont, its next-generation, low-power x86 microarchitecture promising significant IPC (instructions per cycle) gains gen-over-gen compared with Intel’s prior low-power x86 architectures.

Tremont is aimed at compact, low-power packages and innovative form factors for client devices, creative applications for the internet of things (IoT), data center products, etc.

Tremont is integrated within a wider set of silicon IPs in Lakefield, which will power innovative devices like the recently announced dual-screen Microsoft Surface Neo. Iy includes several advancements in ISA (instruction set architecture), microarchitecture, security and power management. Specifically, Tremont’s unique 6-wide (2x3-wide clustered) out-of-order decoder in the front end allows for a more efficient feed to the wider back end, which is fundamental for performance.

The announcement was made at this week's Linley Fall Processor Conference 2019 in Silicon Valley.

https://newsroom.intel.com/wp-content/uploads/sites/11/2019/10/introducing-intel-tremont-microarchiture.pdf