Rambus taped out its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications.
Rambus said its 112G XSR SerDes PHY represents the latest advancement in high-speed signaling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.
"As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances," said Shane Rau, research vice president, computing semiconductors at IDC. "SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity."
“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”
The Rambus 112G XSR SerDes PHY includes:
- High-bandwidth connectivity greater than 800 Gbps per millimeter of beachfront making it ideal for D2D and D2OE interconnects in networking and HPC applications
- Designed to provide a low-power, high-speed interface that supports chip disaggregation
- Best-in-class architecture for power, performance, area (PPA) with approximately 1 pJ/bit or 1mW/Gbps power
- Compliance with Open Interface Forum Common Electrical I/O Consortium (OIF-CEI) standard
