Faraday develops 28G Programmable SerDes at 28nm

Taiwan-based Faraday Technology Corporation announced the availability of its 28Gbps programmable SerDes PHY IP on UMC 28HPC process technology. The device is targeted at 100G Ethernet and most xPON applications.

By adopting the programmable architecture that covers data transfer rates up to 28Gbps, this SerDes IP can readily support the optimization of SoC chip designs from 100Gbps of throughput. On top of that, the IP supports multiple interface standard protocols, such as OIF-CEI, JESD, PCIe Gen1-4, and Ethernet.

“28G SerDes PHY technology has become a crucial building block in addressing a broad range of wired and wireless communication applications,” said Flash Lin, Chief Operating Officer of Faraday. “Faraday's latest 28nm SerDes solution can meet 25/28G SerDes requirements with lower NRE (non-recurring engineering) expense and lower cost compared with other FinFET-based 28G SerDes solutions. By leveraging this solution, we are ready to engage with ASIC customers to reach their potential needs in high-growth networking markets.”

Technical features:

• Supports OIF-CEI-28G VSR/SR and OIF-CEI-25G LR
• Supports PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
• Supports 25Gb to 100Gb Ethernet: 25G/50G/100G-KR4&CR4
• Supports JESD204B/C for high-speed ADC/DAC and FPGA interface
• Supports xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym 10GEPON

http://www.faraday-tech.com