New PCI Express 5.0 spec handles 32 gigatransfers per sec

A newly released PCI Express (PCIe) 5.0 specification reaches 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations.

PCIe 5.0 Specification Highlights

• Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
• Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
• Implements electrical changes to improve signal integrity and mechanical performance of connectors
• Includes new backwards compatible CEM connector targeted for add-in cards
• Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x
• The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.
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“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”

“For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, research fellow at Insight 64. “Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow! We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”