Cadence says ready for TSMC’s 5nm FinFET

Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Cadence said it has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus™ Verification System.

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

http://www.cadence.com/go/tsmc5nmca