Innovium, a start-up based in San Jose, California, announced $77 Million in Series D funding for its high-performance switching silicon for data centers.
The new funding round included investment from Greylock Partners, Walden Everbright, Walden Riverwood Ventures, Paxion Capital, Capricorn Investment Group, Redline Capital, S-Cubed Capital and Qualcomm Ventures. This brings total funding in the company to over $160 million.
“Data center networks are experiencing dramatic traffic growth and face new requirements, driven by public and hybrid cloud, machine learning, analytics, storage and video. Innovium’s grounds-up innovations have enabled a revolutionary platform for a family of products, delivering the industry’s next generation of performance, programmability, cost/bit and robust features. We are excited to significantly increase our investment in Innovium, to help the company accelerate its production, roadmap, and go-to-market efforts,” said Asheem Chandna, Partner at Greylock Partners.
Innovium Unveils 12.8Tbps Data Center Switching Silicon
Innovium said its TERALYNX will be the first single switching chip to break the 10 Tbps performance barrier, along with telemetry, line-rate programmability, the largest on-chip buffers and best-in-class low-latency. The chip is expected to sample in Q3 2017.
TERALYNX includes broad support for 10/25/40/50/100/200/400GbE Ethernet standards. It will deliver 128 ports of 100GbE, 64 ports of 200GbE or 32 ports of 400GbE in a single device. The TERALYNX switch family includes software compatible options at 12.8Tbps, 9.6Tbps, 6.4Tbps and 3.2Tbps performance points, each delivering compelling benefits for switch system vendors and data center operators.
Some highlights:- 12.8Tbps, 9.6Tbps, 6.4Tbps and 3.2Tbps single chip performance options at packet sizes of 300B or smaller
- Single flow performance of 400Gbps at 64B minimum packet size, 4x vs alternatives
- 70MB of on-chip buffer for superior network quality, fewer packet drops and substantially lower latency compared to off-chip buffering options
- Up to 128 ports of 100GbE, 64 ports of 200GbE or 32 ports of 400GbE, which enable flatter networks for lower Capex and fewer hops
- Support for cut-through with best-in-class low latency of less than 350ns
- Programmable, feature-rich INNOFLEX forwarding pipeline
- Comprehensive layer 2/3 forwarding and flexible tunneling including MPLS
- Large table resources with flexible allocation across L2, IPv4 and IPv6
- Line-rate, standards-based programmability to add new/custom features and protocols
- FLASHLIGHT telemetry and analytics to enable autonomous data center networks
- Extensive visibility and telemetry capabilities such as sFlow, FlexMirroring along with highly customizable extra-wide counters
- P4-INT in-band telemetry and extensions to dramatically simplify end to end analysis
- Advanced analytics enable optimal resource monitoring, utilization and congestion control allowing predictive capabilities and network automation
- SERDES I/Os for existing and upcoming networks
- Industry-leading, proven SerDes supports 10G and 25G NRZ, as well as 50G PAM4, to provide customers a variety of connectivity choices, ranging from widely deployed 10/25/40/50/100G Ethernet to upcoming 200/400GbE
- Up to 258 lanes of long-reach SerDes, each of which can be configured dynamically
- Integrated GHz ARM CPU core along with PCIe Gen 3 host connectivity
- ARM core enables development of differentiated real-time automation features
- High speed host connectivity and DMA enhancements enable high performance packet, table and telemetry data transfers while minimizing CPU overhead
- Two high-speed Ethernet ports for management or telemetry dat
