Xilinx Develops 56G PAM4 Transceiver Technology

Xilinx has developed a 16nm FinFET+-based programmable device running 56G transceiver technology using the 4-level Pulse Amplitude Modulation (PAM4) transmission scheme.

Xilinx said PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure.

"Our customers are already anticipating how to accelerate their next generation applications. We recognize the need to raise awareness of 56G PAM4 technology solutions now, to help prepare them to transition their own designs," said Ken Chang, vice president of the SerDes technology group at Xilinx. "I am delighted to be able to showcase our technology."

http://www.xilinx.com