Intel and Cray have been selected to build two next generation, high-performance computing (HPC) systems that will be five to seven times more powerful than the fastest supercomputers today.
Intel will serve as prime contractor to deliver the supercomputers for the U.S. Department of Energy’s (DOE) Argonne Leadership Computing Facility (ALCF). The Aurora system will be based on Intel’s HPC scalable system framework and will be a next-generation Cray “Shasta” supercomputer. Intel said the Aurora system will be delivered in 2018 and have a peak performance of 180 petaflops, making it the world’s most powerful system currently announced to date. Aurora will use future generations of Intel Xeon Phi processors and the Intel Omni-Path Fabric high-speed interconnect technology, a new non-volatile memory architecture and advanced file system storage using Intel Lustre software.
A second system, to be named Theta, will serve as an early production system for the ALCF. To be delivered in the 2016, the system will provide performance of 8.5 petaflops while requiring only 1.7 megawatts of power. The Theta system will be powered by Intel Xeon processors and next-generation Intel Xeon Phi processors, code-named Knights Landing, and will be based on the next-generation Cray XC supercomputer.
“The Aurora system will be one of the most advanced supercomputers ever built, and Cray is honored and proud to be collaborating with two great partners in Intel and Argonne National Lab,” said Peter Ungaro, president and CEO of Cray. “The combination of Cray’s vast experience in building some of the world’s largest and most productive supercomputers, combined with Intel’s cutting-edge technologies will provide the ALCF with a leadership-class system that will be ready for advancing scientific discovery from day one.”
http://newsroom.intel.com/community/intel_newsroom/blog/2015/04/09/chip-shot-intel-selected-by-us-department-of-energy-to-deliver-nations-most-powerful-supercomputer
Intel also disclosed that its Intel Omni-Path Architecture will achieve 100 Gbps line speed and up to 56 percent lower switch fabric latency in medium-to-large clusters than InfiniBand alternatives. The architecture targets a 48 port switch chip compared to the current 36 port InfiniBand alternatives. This will reduce the number of switches required in HPC clusters.
