Xilinx has taped out the semiconductor industry's first 20nm All Programmable device.
Xilinx said the ASIC-class programmable architecture, called UltraScale, was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through 3D ICs. This on-chip architecture will offer massive data flow and routing capabilities.
Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process. Xilinx and TSMC also collaborated on 28nm technologies.
Some highlights of Xilinx UltraScale architecture:
- Massive data flow optimized for wide buses that support multi-terabit throughput
- Multi-region ASIC-like clocking, power management, and next generation security
- Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
- Step function in inter-die bandwidth for 2nd generation 3D IC systems integration
- Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
- Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance
Potential applications for UltraScale devices include 400G OTN systems with intelligent packet processing and traffic management, 4X4 Mixed Mode LTE and WCDMA Radio equipment with smart beamforming, video displays at 4K2K and 8K with smart image enhancement and recognition, high-performance systems for intelligence surveillance and reconnaissance, and high-performance computing applications in data centers.
http://www.xilinx.com/ultrascale