Avago Technologies's new 28nm Serializer/Deserializer (SerDes) core has achieved 32 Gbps performance while withstanding up to 40 dB of channel loss. The company says this level of performance will redefine the data rate feasibility for chip-to-chip, portside and backplane interfaces.
The new 28-nm Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
"Avago has now shipped over 350 million embedded SerDes channels in high performance ASICs and ASSPs,” said Frank Ostojic, vice president and general manager of the ASIC/ASSP Products Division at Avago. “With our latest SerDes milestone, Avago continues to provide early access to IP that enables the development of products that meet today’s requirements for ever increasing bandwidth."
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