NetLogic Debuts Multi-Core Control-Plane Processor for LTE

NetLogic Microsystems introduced its XLP316 multi-core processor featuring a quad-core, 16-issue, 16-threaded, superscalar architecture with out-of-order execution and an L3 cache for control plane processing requirements.



The processor, which runs at up to 2.0GHz, is aimed at communications, networking, storage and security applications. It integrates 16 NXCPUs which are fully cache and memory coherent for software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes. The 16 NXCPUs are efficiently interconnected via NetLogic Microsystems' high-speed, low-latency Enhanced Fast Messaging Network to support billions of in-flight messages and packet descriptors between all on-chip elements. The XLP316 multi-core processor offers a tri-level cache architecture with 4 Mbytes of L3 cache and over 6 Mbytes of fully coherent on-chip cache which delivers 40 Tbps of extremely high-speed on-chip memory bandwidth. The XLP316 processor also incorporates one channel of 72-bit DDR3 interconnect that yields over 100 Gbps of off-chip memory bandwidth.



For 3G/4G LTE equipment, NetLogic said control-plane processing is growing challenge due to the significant growth in signaling traffic from smartphones and tablets. Always-on mobile broadband applications that run on these data-centric devices make frequent connections to the network to check for updates to emails and social networking sites, as well as to perform other background processes. The accumulation of these frequent bursts of signaling traffic is placing an unprecedented burden on control-plane processing that requires new levels of processing horsepower while maximizing energy efficiency in next-generation mobile infrastructure equipment.



Likewise the move to IPv6 is seen as leading to significantly higher control-plane processing requirements. Because IPv6 generates over 28 orders of magnitude more Internet addresses than its predecessor, this dramatically increases the burden on control-plane processing to manage and update the complex IPv6 databases.



To meet these requirements, NetLogic's new processor offers a high-performance floating point unit and a low latency tri-level cache architecture. When compared to competing quad-core processors with dual-issue and single-threading per core, in-order execution and missing L3 cache, the company calculates that its XLP316 delivers up to 400% higher control-plane processing performance, which enables original equipment manufacturers (OEMs) to develop advanced, scalable systems for next-generation LTE and IPv6 networks.
http://www.netlogicmicro.com