Teranetics Announces 40nm Quad 10GBASE-T PHY

Teranetics, a start-up based in San Jose, California, introduced its third generation of 10GBASE-T PHYs implemented in 40nm technology. The small form factor and low power dissipation of the 40nm chips enable 10 GigE copper connections in high-density data center switches. They also pave for 10 GigE LAN-on-motherboard servers.

The Teranetics TN8044 is a quad-port 10GBASE-T PHY device designed for high-density, highly power efficient 10 GigE switches. The TN8022 (dual-port) and TN8020 (single-port) offer the power-efficiency required to enable 10GBASE-T adapter card designs.


Teranetics' new TN8000 family dissipates less than 4 watts per port at a full 100 meters, and as little as 2 watts per port in short reach mode. In addition, this third-generation, 40nm family continues Teranetics' support for triple rate Ethernet (100M/1G/10G). It will also offer support for the emerging Energy Efficient
Ethernet standard (EEE, or IEEE 802.3az). Teranetics CTO and Chairman Sanjay Kasturia is the Editor in chief for the IEEE 802.3az committee developing the EEE standard.


Teranetics noted that its technology further reduces the external component count required to build systems with 10GBASE-T ports. The TN8000 family allows multiple PHYs to share reference clocks and power regulators, and also integrates an EMI filter that previously was built with external components on the PC board. Moreover, MDI
test capabilities reduce manufacturing costs by increasing equipment manufacturers' final yield and decreasing test time.
http://www.teranetics.com