Cortina and Cisco Develop 100 Gbps Chip-to-Chip Interconnects

Cortina Systems and Cisco Systems announced the Interlaken protocol specification: a new technology for high-speed chip-to-chip packet transfers designed to deliver 100 Gbps+ of interchip bandwidth.



The companies said their jointly developed Interlaken protocol builds upon the logical structure of the prevalent SPI4.2, or System Packet Interface Level 4, technology now widely used in networking equipment. It preserves the capabilities of SPI-4.2 with multiple logical channels and back-pressure information, while eliminating its bandwidth ceiling and drastically curtailing its associated pin-count cost. With Interlaken's 90 percent chip-to-chip signal trace improvement, performance is increased while both board and chip design costs are reduced.



Furthermore, Interlaken works with any number of serial lanes uses a highly efficient encoding mechanism with much less overhead than XAUI's 8B/10B. Cortina and Cisco are making the Interlaken specification available with royalty-free licensing to interested parties developing the next generation of gigabit-speed routers and switches.



"Network equipment designs have hit a wall where chip-to-chip interfaces in the data plane are a gating factor limiting the density and overall bandwidth of network equipment," said Mark Gustlin, a technical leader in the Service Provider Routing Technology Group at Cisco Systems.

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