HyperTransport 2.0 Clocks a 75% Performance Boost to 22.4 Gigabytes/second

The HyperTransport Technology Consortium released version 2.0 of the HyperTransport Technology I/O Link Specification, boosting performance 75% to 22.4 Gigabytes/second without significantly changing the electrical specification. HyperTransport is a chip-to-chip interconnect technology that replaces existing multi-level buses in systems such as personal computers, servers, embedded architectures and high performance appliances.


The new HyperTransport Release 2.0 Specification introduces three more powerful bus speeds and mapping to PCI Express, an emerging I/O interconnect architecture. HyperTransport's speed capability extends from the 1.6 Giga Transfers/second (GT/s) of Release 1.1 Specification to 2.0, 2.4, and 2.8 GT/s using dual-data rate clocks at 1.0, 1.2, and 1.4 Gigahertz, delivering a maximum aggregate bandwidth of 22.4 Gigabytes/second. The electrical protocols supporting the new clock rates are backward compatible with all previous versions of the HyperTransport electrical specifications.


HyperTransport technology is being used in products such as Microsoft's Xbox, Apple's Power Mac G5, Cisco's high-end routers, IBM's and Sun Microsystems's servers, notebooks and Tablet PC's based on Transmeta's Efficeon-processor, and all AMD's Athlon64- and Opteron-based PCs, servers and supercomputers. http://www.hypertransport.org