Software-defined memory systems have tremendous potential to accelerate innovation in large data centers. Manoj Wadekar, Hardware Systems Technologist, Meta, shares a perspective on discussions underway at OCP Summit 2022 in San Jose, California.
Showing posts with label Memory. Show all posts
Showing posts with label Memory. Show all posts
Wednesday, October 19, 2022
Tuesday, July 19, 2022
Rambus expands its line of DDR5 memory interface chips
Rambus has expanded its DDR5 memory interface chip portfolio with the addition of the Rambus SPD (Serial Presence Detect) Hub and Temperature Sensor, complementing its Registering Clock Driver (RCD), to deliver high-performance, high-capacity memory solutions for DDR5 computing systems. Both the SPD Hub and Temperature Sensor are critical components on a memory module that sense and report important data for system configuration and thermal management. The SPD Hub is used in both server and client modules, including RDIMMs, UDIMMS and SODIMMS, and the temperature sensor is designed for server RDIMMs.
“The new performance levels of DDR5 memory place an increased premium on signal integrity and thermal management for server and client DIMMs,” said Sean Fan, chief operating officer at Rambus. “With over 30 years of memory subsystem design experience, Rambus is ideally positioned to deliver DDR5 chipset solutions which enable breakthrough bandwidth and capacity for advanced computing systems.”
Key features of the SPD Hub (SPD5118) include:
Key features of the Temperature Sensor (TS5110) include:
“The new performance levels of DDR5 memory place an increased premium on signal integrity and thermal management for server and client DIMMs,” said Sean Fan, chief operating officer at Rambus. “With over 30 years of memory subsystem design experience, Rambus is ideally positioned to deliver DDR5 chipset solutions which enable breakthrough bandwidth and capacity for advanced computing systems.”
Key features of the SPD Hub (SPD5118) include:
- I2C and I3C bus serial interface support Advanced reliability features
- Expanded NVM space for customer-specific applications
- Low latency for fastest I3C bus rates
- Integrated temperature sensor
- Meets or exceeds all JEDEC DDR5 SPD Hub operational requirements (JESD300-5A)
Key features of the Temperature Sensor (TS5110) include:
- Precision thermal sensing I2C and I3C bus serial interface support
- Low latency for fastest I3C bus rates
- Meets or exceeds all JEDEC DDR5 Temperature Sensor operational requirements (JESD302-1.01)
Rambus samples 5600 MT/s DDR5 registering clock driver
Rambus has begun sampling its 5600 MT/s 2nd-generation registering clock driver (RCD) chip to the major DDR5 memory module (RDIMM) suppliers. This new level of performance represents a 17% increase in data rate over the first-generation 4800 MT/s Rambus DDR5 RCD. Rambus said it is able to deliver 5600 MT/s performance at lower latency and power while optimizing timing parameters for improved RDIMM margins.“The RCD is a mission-critical...
Wednesday, October 13, 2021
Rambus samples 5600 MT/s DDR5 registering clock driver
Rambus has begun sampling its 5600 MT/s 2nd-generation registering clock driver (RCD) chip to the major DDR5 memory module (RDIMM) suppliers.
This new level of performance represents a 17% increase in data rate over the first-generation 4800 MT/s Rambus DDR5 RCD.
“The RCD is a mission-critical enabler of DDR5 server DIMMs that provide the bandwidth and capacity needed in next-generation data centers,” said Sean Fan, chief operating officer at Rambus. “Achieving the 5600 MT/s data rate is the latest demonstration of our continued leadership in DDR5 memory interface products.”
Wednesday, March 24, 2021
Samsung's 512GB DDR5 module targets bandwidth-intensive apps
Samsung Electronics began sampling a 512GB DDR5 module based on High-K Metal Gate (HKMG) process technology.
The memory module delivers more than twice the performance of DDR4 at up to 7,200 Mbps, making it suitable for the most high-bandwidth workloads in supercomputing, artificial intelligence (AI) and machine learning (ML), as well as data analytics applications.
Samsung said its DDR5 will utilize highly advanced HKMG technology that has been traditionally used in logic semiconductors. With continued scaling down of DRAM structures, the insulation layer has thinned, leading to a higher leakage current. By replacing the insulator with HKMG material, Samsung’s DDR5 will be able to reduce the leakage and reach new heights in performance. This new memory will also use approximately 13% less power, making it especially suitable for datacenters where energy efficiency is becoming increasingly critical. The HKMG process was adopted in Samsung's GDDR6 memory in 2018 for the first time in the industry. By expanding its use in DDR5, Samsung is further solidifying its leadership in next-generation DRAM technology.
Leveraging through-silicon via (TSV) technology, Samsung’s DDR5 stacks eight layers of 16Gb DRAM chips to offer the largest capacity of 512GB. TSV was first utilized in DRAM in 2014 when Samsung introduced server modules with capacities up to 256GB.
“Samsung is the only semiconductor company with logic and memory capabilities and the expertise to incorporate HKMG cutting-edge logic technology into memory product development,” said Young-Soo Sohn, Vice President of the DRAM Memory Planning/Enabling Group at Samsung Electronics. “By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond.”
“As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud datacenters, networks and edge deployments,” said Carolyn Duran, Vice President and GM of Memory and IO Technology at Intel. “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”
Wednesday, March 25, 2020
Samsung ramps up module manufacturing with extreme ultraviolet tech
Samsung Electronics has shipped one million of the industry's first 10nm-class (D1x) DDR4 (Double Date Rate 4) DRAM modules based on extreme ultraviolet (EUV) technology.
"With the production of our new EUV-based DRAM, we are demonstrating our full commitment toward providing revolutionary DRAM solutions in support of our global IT customers,” said Jung-bae Lee, executive vice president of DRAM Product & Technology at Samsung Electronics. "This major advancement underscores how we will continue contributing to global IT innovation through timely development of leading-edge process technologies and next-generation memory products for the premium memory market."
Samsung said it is the first to adopt EUV in DRAM production to overcome challenges in DRAM scaling. EUV technology reduces repetitive steps in multi-patterning and improves patterning accuracy, enabling enhanced performance and greater yields as well as shortened development time. EUV will be fully deployed in Samsung's future generations of DRAM, starting with its fourth-generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.
"With the production of our new EUV-based DRAM, we are demonstrating our full commitment toward providing revolutionary DRAM solutions in support of our global IT customers,” said Jung-bae Lee, executive vice president of DRAM Product & Technology at Samsung Electronics. "This major advancement underscores how we will continue contributing to global IT innovation through timely development of leading-edge process technologies and next-generation memory products for the premium memory market."Samsung said it is the first to adopt EUV in DRAM production to overcome challenges in DRAM scaling. EUV technology reduces repetitive steps in multi-patterning and improves patterning accuracy, enabling enhanced performance and greater yields as well as shortened development time. EUV will be fully deployed in Samsung's future generations of DRAM, starting with its fourth-generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.
Tuesday, March 19, 2019
Samsung debuts "Flashbolt" High Bandwidth Memory- 3.2 Gbps per pin
Samsung Electronics Co. announced its new High Bandwidth Memory (HBM2E) which promises to deliver the highest DRAM performance levels for use in next-generation supercomputers, graphics systems, and artificial intelligence (AI).
The new Flashbolt DRAM is the industry’s first HBM2E to deliver a 3.2 Gbps data transfer speed per pin, which is 33 percent faster than the previous-generation HBM2.
Flashbolt has a density of 16Gb per die, double the capacity of the previous generation. With these improvements, a single Samsung HBM2E package will offer a 410 gigabytes-per-second (GBps) data bandwidth and 16GB of memory.
“Flashbolt’s industry-leading performance will enable enhanced solutions for next-generation data centers, artificial intelligence, machine learning, and graphics applications,” said Jinman Han, senior vice president of Memory Product Planning and Application Engineering Team at Samsung Electronics. “We will continue to expand our premium DRAM offering, and improve our ‘high-performance, high capacity, and low power’ memory segment to meet market demand.”
The new Flashbolt DRAM is the industry’s first HBM2E to deliver a 3.2 Gbps data transfer speed per pin, which is 33 percent faster than the previous-generation HBM2.Flashbolt has a density of 16Gb per die, double the capacity of the previous generation. With these improvements, a single Samsung HBM2E package will offer a 410 gigabytes-per-second (GBps) data bandwidth and 16GB of memory.
“Flashbolt’s industry-leading performance will enable enhanced solutions for next-generation data centers, artificial intelligence, machine learning, and graphics applications,” said Jinman Han, senior vice president of Memory Product Planning and Application Engineering Team at Samsung Electronics. “We will continue to expand our premium DRAM offering, and improve our ‘high-performance, high capacity, and low power’ memory segment to meet market demand.”
Wednesday, March 13, 2019
Samsung intros 12GB DRAM for mobiles
Samsung Electronics Co. announced mass production of the industry’s first 12-gigabyte (GB) low-power double data rate 4X (LPDDR4X) package -- the highest-capacity mobile DRAM to date.
"With mass production of the new LPDDR4X, Samsung is now providing a comprehensive lineup of advanced memory to power the new era of smartphones, from 12GB mobile DRAM to 512GB eUFS 3.0 storage," said Sewon Chun, executive vice president of Memory Marketing at Samsung Electronics. "Moreover, with the LPDDR4X, we’re strengthening our position as the premium mobile memory maker best positioned to accommodate rapidly growing demand from global smartphone manufacturers."
The 12GB capacity was achieved by combining six 16-gigabit (Gb) LPDDR4X chips based on the second-generation 10nm-class (1y-nm) process into a single package. The new 12GB mobile memory delivers a data transfer rate of 34.1GB per second while minimizing the increase in power consumption inevitably caused by a boost in DRAM capacity.
"With mass production of the new LPDDR4X, Samsung is now providing a comprehensive lineup of advanced memory to power the new era of smartphones, from 12GB mobile DRAM to 512GB eUFS 3.0 storage," said Sewon Chun, executive vice president of Memory Marketing at Samsung Electronics. "Moreover, with the LPDDR4X, we’re strengthening our position as the premium mobile memory maker best positioned to accommodate rapidly growing demand from global smartphone manufacturers."The 12GB capacity was achieved by combining six 16-gigabit (Gb) LPDDR4X chips based on the second-generation 10nm-class (1y-nm) process into a single package. The new 12GB mobile memory delivers a data transfer rate of 34.1GB per second while minimizing the increase in power consumption inevitably caused by a boost in DRAM capacity.
Wednesday, January 16, 2019
Photonic memory research at Eindhoven University of Technology
Researchers of the Institute of Photonic Integration of the Eindhoven University of Technology are developing a hybrid memory that combines photonic properties and magnetic hard drives.
The idea is to use femtosecond light pulses to write data directly in a magnetic memory.
"The switching of the magnetization direction using the single-pulse all-optical switching is in the order of picoseconds, which is about a 100 to 1000 times faster than what is possible with today's technology. Moreover, as the optical information is stored in magnetic bits without the need of energy-costly electronics, it holds enormous potential for future use in photonic integrated circuits," states Mark Lalieu, Ph.D. candidate at the Applied Physics Department of TU/e.
https://www.tue.nl/en/news/news-overview/10-01-2019-next-generation-photonic-memory-devices-are-light-written-ultrafast-and-energy-efficient/
The idea is to use femtosecond light pulses to write data directly in a magnetic memory."The switching of the magnetization direction using the single-pulse all-optical switching is in the order of picoseconds, which is about a 100 to 1000 times faster than what is possible with today's technology. Moreover, as the optical information is stored in magnetic bits without the need of energy-costly electronics, it holds enormous potential for future use in photonic integrated circuits," states Mark Lalieu, Ph.D. candidate at the Applied Physics Department of TU/e.
https://www.tue.nl/en/news/news-overview/10-01-2019-next-generation-photonic-memory-devices-are-light-written-ultrafast-and-energy-efficient/
Thursday, July 19, 2018
Samsung develops 8-gigabit LPDDR5 DRAM for 5G mobile devices
Samsung Electronics is ready to begin mass production of the first 10-nm class 8-gigabit LPDDR5 DRAM for use in upcoming 5G and Artificial Intelligence (AI)-powered mobile applications including smartphones and automobiles.
The 10nm-class LPDDR5 DRAM will be available in two bandwidths – 6,400Mb/s at a 1.1 operating voltage (V) and 5,500Mb/s at 1.05V.
The new memory incorporates a number of innovations including to lower its voltage in accordance with the operating speed of the corresponding application processor, when in active mode. There is also a deep sleep mode which cuts power to approximately half of the idle mode. Samsung estimates power savings of up to 30% over the previous generation.
The newly-developed 8Gb LPDDR5 is the latest addition to Samsung’s premium DRAM lineup, which includes 10nm-class 16Gb GDDR6 DRAM (in volume production since December 2017) and 16Gb DDR5 DRAM (developed in February).
“This development of 8Gb LPDDR5 represents a major step forward for low-power mobile memory solutions,” said Jinman Han, senior vice president of Memory Product Planning & Application Engineering at Samsung Electronics. “We will continue to expand our next-generation 10nm-class DRAM lineup as we accelerate the move toward greater use of premium memory across the global landscape.”
The 10nm-class LPDDR5 DRAM will be available in two bandwidths – 6,400Mb/s at a 1.1 operating voltage (V) and 5,500Mb/s at 1.05V.
The new memory incorporates a number of innovations including to lower its voltage in accordance with the operating speed of the corresponding application processor, when in active mode. There is also a deep sleep mode which cuts power to approximately half of the idle mode. Samsung estimates power savings of up to 30% over the previous generation.
The newly-developed 8Gb LPDDR5 is the latest addition to Samsung’s premium DRAM lineup, which includes 10nm-class 16Gb GDDR6 DRAM (in volume production since December 2017) and 16Gb DDR5 DRAM (developed in February).
“This development of 8Gb LPDDR5 represents a major step forward for low-power mobile memory solutions,” said Jinman Han, senior vice president of Memory Product Planning & Application Engineering at Samsung Electronics. “We will continue to expand our next-generation 10nm-class DRAM lineup as we accelerate the move toward greater use of premium memory across the global landscape.”
Tuesday, May 29, 2018
Samsung hits mass production of 10nm-Class 32GB DDR4
Samsung Electronics Co. started mass producing the industry’s first 32-gigabyte (GB) double data rate 4 (DDR4) memory.
The small outline dual in-line memory modules (SoDIMMs) are used in gaming laptops.
Samsung said that compared to its 16GB SoDIMM based on 20nm-class 8-gigabit (Gb) DDR4, which was introduced in 2014, the new 32GB module doubles the capacity while being 11 percent faster and approximately 39 percent more energy efficient. A 64GB laptop configured with two 32GB DDR4 modules consumes less than 4.6 watts (W) in active mode and less than 1.4W when idle.
The small outline dual in-line memory modules (SoDIMMs) are used in gaming laptops.Samsung said that compared to its 16GB SoDIMM based on 20nm-class 8-gigabit (Gb) DDR4, which was introduced in 2014, the new 32GB module doubles the capacity while being 11 percent faster and approximately 39 percent more energy efficient. A 64GB laptop configured with two 32GB DDR4 modules consumes less than 4.6 watts (W) in active mode and less than 1.4W when idle.
Tuesday, April 3, 2018
Kingston intros consumer-grade PCIe NVMe SSD using 3D NAND
Kingston Digital introduced a line of entry-level consumer-grade PCIe NVMe SSD utilizing 3D NAND for notebooks and desktop. The drive is available in 240GB, 480GB and 960GB2 capacities,
The single-sided M.2 2280 (22mm x 80mm) form factor makes SSD features a Gen 3.0 x2 interface, 4-channel Phison 5008 controller, and 3D NAND Flash. It delivers 2x the performance of SATA SSDs with read/write speeds up to 1500MB/s and 1000MB/s.
Some key specs
Interface: PCIe NVMe Gen 3.0 x2 Lanes
Controller: Phison 5008
NAND: 3D TLC
Sequential Read/Write:
Random 4K Read/Write:
MTBF: 1 million hours
The single-sided M.2 2280 (22mm x 80mm) form factor makes SSD features a Gen 3.0 x2 interface, 4-channel Phison 5008 controller, and 3D NAND Flash. It delivers 2x the performance of SATA SSDs with read/write speeds up to 1500MB/s and 1000MB/s.Some key specs
Interface: PCIe NVMe Gen 3.0 x2 Lanes
Controller: Phison 5008
NAND: 3D TLC
Sequential Read/Write:
- 240GB: up to 1,500/800MB/s
- 480GB: up to 1,500/900MB/s
- 960GB: up to 1,500/1,000MB/s
Random 4K Read/Write:
- 240GB: up to 100,000/80,000MB/s
- 480GB: up to 100,000/90,000MB/s
- 960GB: up to 120,000/100,000MB/s
MTBF: 1 million hours
Monday, January 22, 2018
Integral Memory debuts 512GB microSDXC card
Integral Memory plc is introducing a 512GB microSDXC V10 UHS-I U1 memory card.
The new card meets the Video Speed Class 10 (V10) standard, ensuring fast data transfer of Full HD video on devices including digital cameras, action cams, drones and camcorders.
http://www.integralmemory.com
The new card meets the Video Speed Class 10 (V10) standard, ensuring fast data transfer of Full HD video on devices including digital cameras, action cams, drones and camcorders.
http://www.integralmemory.com
Wednesday, January 17, 2018
Samsung ramps 16-Gigabit GDDR6 for advanced graphics
Samsung Electronics Co. has commenced mass production of the industry’s first 16-gigabit (Gb) Graphics Double Data Rate 6 (GDDR6) memory for use in advanced graphics processing for gaming devices and graphics cards as well as automotive, network and artificial intelligence systems.
Samsung's new 16Gb GDDR6 memory is built on advanced 10-nanomter (nm) class process technology, and performs at an 18-gigabits-per-second (Gbps) pin speed with data transfers of 72 gigabytes per second (GBps), which represents a more than two-fold increase over 8Gb GDDR5 with its 8Gbps pin speed.
Samsung's new 16Gb GDDR6 memory is built on advanced 10-nanomter (nm) class process technology, and performs at an 18-gigabits-per-second (Gbps) pin speed with data transfers of 72 gigabytes per second (GBps), which represents a more than two-fold increase over 8Gb GDDR5 with its 8Gbps pin speed.
Thursday, July 14, 2016
Toshiba and WD Inaugurate Flash Memory Fab in Japan
Toshiba and Western Digital celebrated the opening of the New Fab 2 semiconductor fabrication facility located in Yokkaichi, Mie Prefecture, Japan.
The new facility will support the conversion of the companies’ 2D NAND capacity to 3D flash memory, allowing realization of solutions offering higher densities and better device performance. Construction began in September 2014.
Satoshi Tsunakawa, President and CEO of Toshiba Corporation, said, “Advanced technologies underline our commitment to respond to continued demand as an innovator in flash memory. We are enhancing manufacturing efficiency and the quality of our world-class facility. Building on that, we also plan investments of as much as 860 billion yen by FY2018, in line with the market situation. Our commitment is firm, and we are confident that our joint venture with Western Digital will produce cost competitive next generation memories at Yokkaichi.”
http://www.toshiba.com
The new facility will support the conversion of the companies’ 2D NAND capacity to 3D flash memory, allowing realization of solutions offering higher densities and better device performance. Construction began in September 2014.Satoshi Tsunakawa, President and CEO of Toshiba Corporation, said, “Advanced technologies underline our commitment to respond to continued demand as an innovator in flash memory. We are enhancing manufacturing efficiency and the quality of our world-class facility. Building on that, we also plan investments of as much as 860 billion yen by FY2018, in line with the market situation. Our commitment is firm, and we are confident that our joint venture with Western Digital will produce cost competitive next generation memories at Yokkaichi.”
http://www.toshiba.com
Saturday, June 11, 2016
HPE Brings The Machine to Open Source community
HPE intends to support open source software on its futuristic platform billed as "The Machine." The company announced its intent to bring The Machine to open source developers very early in the software development cycle.
The Machine, which has been a long-term research project of HP Labs, promises to overturn 60-years of processor-centric platforms with a new paragidm based on memory-centric architecture.
HP said it will start familiarizing developers with its new programming model as well as invite them to help develop the software itself. An initial release of developer tools is expected in the coming month, including the following four contributions of code:
HPE is also planning changes to Linux that enable it to run on The Machine, as well as example applications that demonstrate how The Machine can significantly improve application scale and performance.
http://www.hpe.com
The Machine, which has been a long-term research project of HP Labs, promises to overturn 60-years of processor-centric platforms with a new paragidm based on memory-centric architecture.
HP said it will start familiarizing developers with its new programming model as well as invite them to help develop the software itself. An initial release of developer tools is expected in the coming month, including the following four contributions of code:
- Fast optimistic engine for data unification services: A completely new database engine that speeds up applications by taking advantage of a large number of CPU cores and non-volatile memory (NVM).
- Fault-tolerant programming model for non-volatile memory: Adapts existing multi-threaded code to store and use data directly in persistent memory. Provides simple, efficient fault-tolerance in the event of power failures or program crashes.
- Fabric Attached Memory Emulation: An environment designed to allow users to explore the new architectural paradigm of The Machine.
- Performance emulation for non-volatile memory bandwidth: A DRAM-based performance emulation platform that leverages features available in commodity hardware to emulate different latency and bandwidth characteristics of future byte-addressable NVM technologies.
HPE is also planning changes to Linux that enable it to run on The Machine, as well as example applications that demonstrate how The Machine can significantly improve application scale and performance.
http://www.hpe.com
Monday, April 4, 2016
Samsung: First 10-Nanometer Class DRAM Enters Production
Samsung Electronics announced the start of mass production of the industry’s first 10-nanometer (nm) class, 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. The milestone is expected to accelerate the industry-wide shift to advanced DDR4 products.
The production of Samsung's 10nm-class DRAM uses ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.
“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”
The new DRAM supports a data transfer rate of 3,200 Mbps, which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.
http://www.samsung.com
The production of Samsung's 10nm-class DRAM uses ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.
“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”
The new DRAM supports a data transfer rate of 3,200 Mbps, which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.
http://www.samsung.com
Monday, June 23, 2014
Micron Collaborates with Intel on Knights Landing
Micron Technology is working with Intel to deliver an on-package memory solution for Intel's next-generation Xeon Phi processor, codenamed Knights Landing. The on-going collaboration leverages fundamental DRAM and stacking technologies also found in Micron's Hybrid Memory Cube products.
The on package memory combines high-speed logic and DRAM layers into one optimized package that will set a new industry benchmark for performance and energy efficiency. Intel said Knights Landing will deliver 5X the sustained memory bandwidth versus DDR4 with one-third the energy per bit in half the footprint.
"Intel's many integrated cores (MIC) architecture and Micron's high performance memory is a formidable combination," said Tom Eby, vice president for Micron's compute and networking business unit. "Intel's and Micron's advanced technologies successfully marry the processor to a memory system that delivers the very rare coupling of low power and extreme bandwidth."
"The next-generation Intel® Xeon Phi processor, codenamed Knights Landing, will launch with up to 16GB of high performance, on-package memory that delivers dramastically improved the sustained memory bandwidth versus DDR4 and brings tremendous power-efficiency and space-savings. It is the first Intel HPC processor to use this new high performance on package memory," said Charles Wuischpard, Vice President, General Manager, Workstations and High Performance Computing Data Center Group at Intel. "This will allow the world's leading researchers, scientists, and engineers to run larger workloads faster while maintaining current code investments. We're pleased to be working with Micron to deliver it."
http://investors.micron.com/releasedetail.cfm?ReleaseID=856057
More on Micron's Hybrid Memory Cube
The on package memory combines high-speed logic and DRAM layers into one optimized package that will set a new industry benchmark for performance and energy efficiency. Intel said Knights Landing will deliver 5X the sustained memory bandwidth versus DDR4 with one-third the energy per bit in half the footprint.
"Intel's many integrated cores (MIC) architecture and Micron's high performance memory is a formidable combination," said Tom Eby, vice president for Micron's compute and networking business unit. "Intel's and Micron's advanced technologies successfully marry the processor to a memory system that delivers the very rare coupling of low power and extreme bandwidth."
"The next-generation Intel® Xeon Phi processor, codenamed Knights Landing, will launch with up to 16GB of high performance, on-package memory that delivers dramastically improved the sustained memory bandwidth versus DDR4 and brings tremendous power-efficiency and space-savings. It is the first Intel HPC processor to use this new high performance on package memory," said Charles Wuischpard, Vice President, General Manager, Workstations and High Performance Computing Data Center Group at Intel. "This will allow the world's leading researchers, scientists, and engineers to run larger workloads faster while maintaining current code investments. We're pleased to be working with Micron to deliver it."
http://investors.micron.com/releasedetail.cfm?ReleaseID=856057
More on Micron's Hybrid Memory Cube
