Rambus delivers PCIe 6.0 subsystem supporting CXL

Rambus released its PCI Express (PCIe) 6.0 Interface Subsystem comprised of PHY and controller IP. 

The Rambus PCIe 6.0 Interface Subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling.

Key features of the Rambus PCIe 6.0 Interface Subsystem include:

• Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
• Implements low-latency Forward Error Correction (FEC) for link robustness
• Supports fixed-sized FLITs that enable high-bandwidth efficiency
• Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
• State-of-the-art security with an IDE engine (controller)
• Supports CXL 3.0 for new use models that optimize memory resources (PHY)

“The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance,” said Scott Houghton, general manager of Interface IP at Rambus. “The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with premier latency, power, area and security.”

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PCIe 7.0 spec doubles data rate to 128 GT/s

The PCI Express (PCIe) 7.0 specification will double the data rate to 128 GT/s (giga transfers per second) and up to 512 GB/s bi-directionally via x16 configuration.

PCI-SIG aims to release the updated spec in 2025.

PCI-SIG technical workgroups will be developing the PCIe 7.0 specification with the following feature goals:

• Delivering 128 GT/s raw bit rate 
• Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
• Focusing on the channel parameters and reach
• Continuing to deliver the low-latency and high-reliability targets
• Improving power efficiency
• Maintaining backwards compatibility with all previous generations of PCIe technology

“For 30 years the guiding principle of PCI-SIG has been, ‘If we build it, they will come,’” observed Nathan Brookwood, Research Fellow at Insight 64. “Early parallel versions of PCI technology accommodated speeds of hundreds of megabytes/second, well matched to the graphics, storage and networking demands of the 1990s. In 2003, PCI-SIG evolved to a serial design that supported speeds of gigabytes/second to accommodate faster solid-state disks and 100MbE Ethernet. Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. Today’s announcement of PCI-SIG’s plan to double the channel’s speed to 512 GB/s (bi-directionally) puts it on track to double PCIe specification performance for another 3-year cycle.”

“With the forthcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation,” said Al Yanes, PCI-SIG President and Chairperson. “As PCIe technology continues to evolve to meet the high bandwidth demands, our workgroups’ focus will be on channel parameters and reach and improving power efficiency.”

https://www.pcisig.com

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Renesas intros PCIe Gen6 clock buffers and multiplexers

Renesas Electronics introduced the first clock buffers and multiplexers that meet stringent PCIe Gen6 specifications. 

Renesasis offering 11 new clock buffers and 4 new multiplexers. The new devices, which also support and provide extra margin for PCIe Gen5 implementations, complement Renesas’ low-jitter 9SQ440, 9FGV1002 and 9FGV1006 clock generators to offer customers a complete PCIe Gen6 timing solution for data center/cloud computing, networking and high-speed industrial applications.

The PCIe Gen6 standard supports extremely high data rates of 64 GT/s while requiring very low clock jitter performance of less than 100fs RMS. Renesas’ new RC190xx clock buffers and RC192xx multiplexers have PCIe Gen6 additive jitter specs of only 4fs RMS, making them virtually noiseless, and thereby future-proofing customer designs for the next generation of industry standards.

“PCIe Gen6 timing will be at the heart of new equipment in data centers, high-speed networking and other applications,” said Zaher Baidas, Vice President of the Timing Products Division at Renesas. “As we have done for preceding generations, Renesas is providing customers with the first timing solution to enable these new, higher-performance systems. Our customers know that we have the technical expertise and market knowledge to ensure that their products will be able to meet future requirements as well.”

https://www.renesas.com/us/en/products/clocks-timing

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Synopsys announces PCIe 6.0 solutions

Synopsys introduced its intellectual property solution for PCI Express (PCIe) 6.0 technology that includes controller, PHY and verification IP.

The solutions enables early development of PCIe 6.0 system-on-chip (SoC) designs. 

Synopsys' DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

"Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "With Synopsys' complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys' proven expertise and established leadership in PCI Express to accelerate their path to silicon success."

The DesignWare Controller and PHY IP for PCIe 6.0 early access are scheduled to be available in Q3 of 2021. The Verification IP for PCIe 6.0 is available now. 

https://www.synopsys.com/designware-ip/interface-ip/pci-express/pci-express-6.html

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Work continues on PCIe 6.0

PCI-SIG posted a new PCI Express Base Specification Revision 6.0, Version 0.3 for review by its membership.

PCI Express (PCIe) 6.0 technology will double the data rate to 64 GT/s while maintaining backwards compatibility with previous generations. PCI-SIG, which is the consortium that owns and manages PCI specification, said PCIe 6.0 is on target for release in 2021.

PCIe 6.0 Specification Features

• Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
• Utilizes PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and leverages existing 56G PAM-4 in the industry
• Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
• Maintains backwards compatibility with all previous generations of PCIe technology

https://pcisig.com/

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TE debuts PCIe Gen 4 card edge connectors supporting 16 Gbps

TE Connectivity (TE) introduced its new PCIe Gen 4 card edge connectors, which meet industry PCI-SIG Card Electromechanical (CEM) specification 4.0 and support Intel and AMD next-generation platforms with up to 16 Gbps of bandwidth.

The new connectors support next-generation CPUs for better system application scaling and higher bandwidth in servers, storage, workstations and desktop PCs.

TE’s new PCIe Gen 4 card edge connectors feature a 1.00mm pitch to enable all generations of PCI Express signaling designs and support speeds of 16 Gbps (PCIe Gen 4), 8.0 Gbps (PCIe Gen 3), 5.0 Gbps (PCIe Gen 2) and 2.5 Gbps (PCIe Gen 1). In addition, the connectors’ footprint and mating interface are backward-compatible with each PCIe generation.

“As manufacturers begin to implement PCIe Gen 4 connectivity inside their data center products, they may require high-performing card edge connectors that offer full backward compatibility,” said Taylor Luo, product manager at TE Connectivity. “TE’s new PCIe Gen 4 adapters fully support new designs for Intel, AMD and IBM platforms and are available in a wide range of configurations to address virtually any need.”

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New PCI Express 5.0 spec handles 32 gigatransfers per sec

A newly released PCI Express (PCIe) 5.0 specification reaches 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations.

PCIe 5.0 Specification Highlights

• Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
• Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
• Implements electrical changes to improve signal integrity and mechanical performance of connectors
• Includes new backwards compatible CEM connector targeted for add-in cards
• Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x
• The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.
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“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”

“For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, research fellow at Insight 64. “Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow! We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”

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NEC Debuts ExpEther 40G, Connecting PCIe Devices over Ethernet

NEC announced the general availability in North America of its ExpEther 40G technology as an advanced version of ExpEther 1G/10G.

The ExpEther technology enables system expansion by connecting PCI Express devices directly, using an Ethernet infrastructure. As the ExpEther keeps the native PCI Express connectivity, the PCI Express devices can also be operated as a single system, despite being distributed in different locations connected by Ethernet. This process enables standard PCI Express configurations, interruptions, and hot plugging to be remotely performed with an Ethernet LAN, as if they were connected to a virtual single-hop PCI Express switch.

NEC said its ExpEther 40G technology delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. NEC has closely collaborated with Xilinx, a fellow ExpEther Consortium member, to validate and enable the ExpEther 40G technology as either an IP core or an ExpEther platform leveraging Xilinx UltraScale FPGAs. NEC launched the IP core business in January 2016.

NEC hopes to develop additional business opportunities by collaborating with OpenPOWER foundation members IBM and Xilinx to increase the scalability of ExpEther technology and the Power8 Processor.

http://www.expether.org/
https://www.necam.com/

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Avago Positions PCIe Switching for Data Center Systems

Avago Technologies announced full production of its PEX9700 Series of 3rd generation PCIe switching silicon for the convergence of servers, storage, and network devices in data centers.

PCIe delivers performance of up to 1.5Tb/s through 97 lanes in full-duplex mode.

The Avago ExpressFabric PEX9700 series of switches simplify connectivity of data center systems, delivering the highest PCIe switching performance available inside the rack.

Avago said that while PCIe is the ubiquitous interconnect for internal devices, external device connectivity typically requires using other architectures. This wastes power, reduces performance, and increases costs. With these PCIe switches, devices within a hyperscale system, NVMe enclosure, and rack-scale-based subsystems can now communicate directly through the same high-performance PCIe fabric, turning those devices into a single high-performance, high-capacity compute system.

PEX9700 key new switching features include:

• Shared I/O - Enables endpoints to be shared among multiple hosts to maximize system resource efficiency and reduce cost and power
• Tunneled Windows Connection - Interconnect up to 24 (+1 management host) nodes on a single chip or cascade multiple chips to connect up to 72 nodes with no performance loss
• Embedded DMA Engines - Equips each port with a NIC-DMA engine that enables efficient data transfers between multiple hosts
• Flexible Port Configuration - Allows up to 23 endpoints to be combined with ports as wide as 16 lanes, providing nearly 16GB/s of bandwidth on each link
• Downstream Port Containment - Isolates errors in any endpoint from bringing down the entire system
• Dedicated Port Management - Enables software control of switch features for customized implementations using Avago-developed software modules

"PCIe is fundamental to next-generation data centers to manage the growth and complexity of data traffic," said Tom Swinford, senior vice president and general manager, Data Center Solutions Group at Avago. "With PCIe technology at the core of nearly every product in the data center, fabric convergence within the rack using Avago ExpressFabric is a powerful approach for intra-rack connectivity to enable powerful performance and scaling of systems."

http://www.avagotech.com/

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Intel Rolls Out Solid-State Drives for PCIe

Intel announced a new family of Solid-State Drives (SSD) for PCIe and aimed at data centers.

Thew new drives boast substantial performance gains over SATA SSDs and traditional hard disk drives -- Intel claims up to six times faster data transfer speed than 6 Gbps SAS/SATA SSDs. Specifically, the Intel Solid-State Drive Data Center P3700 Series (460K IOPS), can replace the performance of 7 SATA SSDs aggregated through a host bus adapter (HBA) (approximately 500K IOPS).

The new drives are based on Intel-developed controller, firmware, and leading manufacturing process NAND flash memory. Drive capacities range from 400GB to 2.0TB.

http://www.intel.com/content/www/us/en/solid-state-drives/intel-ssd-dc-family-for-pcie.html

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