Samsung's 2nd gen SmartSSD computational drive offloads CPU

Samsung Electronics introduced a second generation of its pioneering SmartSSD computational storage drive that uses a Xilinx Versal Adaptive chip to offload certain data processing functionality from the host CPU.

Unlike existing SSDs, Samsung’s SmartSSD can process data directly, thereby minimizing data transfers between the CPU, GPU and RAM. This technology can avoid the bottlenecks that often occur when moving data between storage devices and CPUs, resulting in markedly improved system performance and much higher energy efficiency.

 Samsung says that compared to conventional data center solid-state drives, processing time for scan-heavy database queries can be slashed by over 50%, energy consumption by up to 70% and CPU utilization by up to 97%.

Since its development in 2020 through the joint efforts of Samsung and AMD, the first-generation SmartSSD is being supplied to global IT companies including video communications platform providers. The first-generation SmartSSD was recognized as an Innovation Awards Honoree at CES 2021 for its outstanding performance and energy efficiency.

 “Commercialization of the first-generation SmartSSD, in collaboration with AMD, established that the computational storage market has great potential,” said Jin-Hyeok Choi, Executive Vice President and Head of Memory Solution Product & Development at Samsung Electronics. “With the upgraded processing functionality of the second-generation SmartSSD, Samsung will be able to easily address increasing customer needs in the database and video transcoding sectors, as we expand the boundaries of the next-generation storage market.”

 “Powered by Xilinx Versal Adaptive SoCs from AMD, second-generation Samsung SmartSSDs enable improved CPU efficiency and greatly reduced energy consumption by efficiently integrating the computing and storage functions in data centers,” said Sina Soltani, Corporate Vice President of Sales, AECG, Data Center and Communication Group at AMD. “As data-intensive applications continue to grow, second-generation Samsung SmartSSDs will deliver the superior performance and efficiency required for this expanding market.”

 https://news.samsung.com/global/samsung-electronics-develops-second-generation-smartssd-computational-storage-drive-with-upgraded-processing-functionality

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AMD to acquire Pensando for its DPU + software stack

AMD agreed to acquire Pensando, a Silicon Valley start-up offering a software-defined edge services platform powered by a custom packet processor, for approximately $1.9 billion before working capital and other adjustments. 

Pensando ("thinking" in Spanish) is led by Cisco’s legendary “MPLS” team — Mario Mazzola, Prem Jain, Luca Cafiero, Soni Jiandani and Randy Pond. Its platform is designed to accelerate networking, security, storage and other services for cloud, enterprise and edge applications. Its architecture leverages the programmable packet processor distributed throughout a network to efficiently accelerate multiple infrastructure services simultaneously, offloading workloads from the CPU and increasing overall system performance. The company says it can achieve between 8x and 13x greater performance compared to competitive solutions.

Pensando claims multiple deployments at scale across cloud and enterprise customers, including Goldman Sachs, IBM Cloud, Microsoft Azure and Oracle Cloud. 

“To build a leading-edge data center with the best performance, security, flexibility and lowest total cost of ownership requires a wide range of compute engines,” said Dr. Lisa Su, AMD chair and CEO. “All major cloud and OEM customers have adopted EPYC processors to power their data center offerings. Today, with our acquisition of Pensando, we add a leading distributed services platform to our high-performance CPU, GPU, FPGA and adaptive SoC portfolio. The Pensando team brings world-class expertise and a proven track record of innovation at the chip, software and platform level which expands our ability to offer leadership solutions for our cloud, enterprise and edge customers.”

“We are excited to join the AMD family. Our shared cultures of innovation, excellence and relentless focus on partners and customers make this an ideal combination. Together, we have the talent and tools to deliver on our customers’ vision for the future of computing,” said Pensando CEO Prem Jain. “In less than five years Pensando has assembled a best-in-class engineering team that are experts in building systems together with a rich, deep ecosystem of partners and customers who have currently deployed over 100,000 Pensando platforms into production. Joining together with AMD will help accelerate growth in our core business and enable us to pursue a much larger customer base across more markets.”

“Industry leadership is based on catching business model disruptions enabled by new technologies,” said John Chambers, chair of the board of Pensando. "Pensando is built upon strong customer relationships and a solution that is at least two years ahead in cloud, edge and enterprise. For example, the performance and scale of Pensando’s distributed services platform is 8x-13x of the largest cloud provider and uses less power. Pensando’s smart switching architecture has 100x the scale, 10x the performance at one-third the cost of ownership of any comparable products in the enterprise market.  Pensando’s leadership position in software-defined cloud, compute, networking, security and storage services as part of the much larger AMD portfolio is in my opinion a perfect fit to shape the data center computing landscape for the next decade.”

CEO Prem Jain and the Pensando team will join AMD as part of the Data Center Solutions Group, led by AMD Senior Vice President and General Manager Forrest Norrod. Pensando will remain focused on executing their product and technology roadmaps, now with additional scale to accelerate their business and address growing market opportunities across a broader number of customers.

http://pensando.io

Pensado emerges from stealth, led by "MPLS" team from Cisco

Wednesday, October 16, 2019  Edge, Start-Ups  

Pensando Systems, a start-up based in San Jose, California, emerged from stealth to unveil its first product -- a software-defined edge services platform that was developed in collaboration with the world’s largest cloud, enterprise, storage, and telecommunications companies.

Pensando ("thinking" in Spanish) is led by Cisco’s legendary “MPLS” team — Mario Mazzola, Prem Jain, Luca Cafiero, Soni Jiandani and Randy Pond. Hewlett Packard Enterprise and Lightspeed Venture Partners led a Series C round to raise up to $145 million in funding. This will bring the total amount raised to $278 million after an earlier founder-led series A round of $71 million, and a customer-led series B round of $62 million. Cited customers, investors, and partners including HPE, Goldman Sachs, NetApp, and Equinix.

The Pensando platform is a custom programmable processor optimized to execute a software stack delivering cloud, compute, networking, storage and security services wherever data is located, all managed via its Venice Centralized Policy and Services Controller. The platform delivers highly programmable software-defined cloud, compute, networking, storage, and security services wherever data is located.


The platform promises an improved security posture through distributed network protection and east-west security. It offloads networking and security functions at wire speed to dedicated accelerators, and it is designed to scale to > 1000 tenants per server and >1M routes.

The company claims its capability means that cloud providers can now gain a technological advantage over the current market leader, Amazon Web Services Nitro, delivering 5-9x improvements in productivity, performance, and scale when compared to current architectures with no risk of lock-in.

The portfolio includes:

• Naples 100 and Naples 25 cards for installation in standard servers. The Naples Distributed Services Card (DSC) delivers high-performance cloud, compute, networking, storage and security functions. 
• Venice Centralized Policy and Services Controller - Centrally-managed enterprise-grade security and visibility at every level of the stack enables seamless distribution of all infrastructure services policies to active Naples nodes. In addition, Venice handles lifecycle management such as deploying in-service software upgrades to Naples nodes and delivers always-on telemetry, deep end-to-end observability, and operational simplicity across the environment. 

Pensando also announced that Mark Potter, chief technology officer of Hewlett Packard Enterprise (HPE), and Barry Eggers, a partner of Lightspeed Venture Partners, joined the board of directors, with John Chambers, CEO of JC2 Ventures, leading as chairman.

http://pensando.io

Are next-gen SmartNICs gaining traction with top cloud providers?

Tuesday, September 21, 2021  Pensando, SmartNICs  

https://youtu.be/fEEFyIJYzXIIn this video, Prem Jain, co-founder and CEO of Pensando, discusses SmartNIC adoption trends by major cloud providers. Hot topics include bare-metal-as-a-service acceleration and virtualized storage. For more insights from industry thought leaders check out: https://nextgeninfra.io/VMware's Project Monterey for SmartNICs - Pensando's perspectiveWednesday, September 30, 2020  Pensando, SmartNICs  Pensando...

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VMware's Project Monterey for SmartNICs - Pensando's perspective

Wednesday, September 30, 2020  Pensando, SmartNICs  

Pensando Systems is working with VMware on Project Monterey to integrate the next generation of SmartNIC technology into fully virtualized enterprise networks.The project aims to rearchitect VMware Cloud Foundation to enable disaggregation of the server including extending support for bare metal servers, thereby allowing physical resources to be dynamically accessed by applications based on policy or via software API.In this video, Silvano Gai of...

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AMD completes acquisition of Xilinx

Monday, February 14, 2022  AMD, Silicon  

AMD completed its previously-announced  acquisition of Xilinx in an all-stock transaction. Xilinx stockholders received 1.7234 shares of AMD common stock and cash in lieu of any fractional shares of AMD common stock for each share of Xilinx common stock.AMD expects the acquisition to be accretive to non-GAAP margins, non-GAAP EPS and free cash flow generation in the first year.Former Xilinx CEO Victor Peng will join AMD as president of the newly...

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Xilinx looks beyond FPGAs with Adaptive Compute Acceleration Platform

Tuesday, October 02, 2018  Xilinx  

At its second annual Xilinx Developer Forum (XDF) in San Jose, Xilinx unveiled strategic moves beyond its mainstay field-programmable gate array (FPGAs) with the introduction of its own accelerator line cards and, more significantly, a new Adaptive Compute Acceleration Platform (ACAP). Xilinx, which got its start in 1984 and now sells a broad range of FPGAs and complex programmable logic devices (CPLDs), is transforming itself into a higher-value...

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Xilinx to acquire Solarflare for SmartNIC solutions

Wednesday, April 24, 2019  Xilinx  

Xilinx agreed to acquire Solarflare Communications, a provider of high-performance, low latency networking solutions for customers spanning FinTech to cloud computing. Financial terms were not disclosed. Xilinx said the acquisition enables it to combine its FPGA, MPSoC and ACAP solutions with Solarflare's ultra-low latency network interface card (NIC) technology and Onload application acceleration software. The target is new converged SmartNIC solutions,...

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Xilinx intros FPGA data center accelerator card for HPC

Xilinx introduced a data center accelerator card and a new standards-based, API-driven clustering solution for deploying FPGAs at massive scale for high performance computing (HPC) and database workloads. 

The new Alveo U55C accelerator, which is Xilinx’s most powerful Alveo accelerator card to date, delivers more parallelism of data pipelines, superior memory management, optimized data movement throughout the pipeline, and the highest performance-per-watt in the Alveo portfolio. The Alveo U55C card is a single-slot full height, half length (FHHL) form factor with a low 150W max power. 

The company says the new card offers superior compute density and doubles the HBM2 to 16GB compared to its predecessor, the dual-slot Alveo U280 card. The U55C provides more compute in a smaller form factor for creating dense Alveo accelerator-based clusters. It’s built for high-density streaming data, high IO math, and big compute problems that require scale-out like big data analytics and AI applications. Leveraging RoCE v2 and data center bridging, coupled with 200 Gbps bandwidth, the API-driven clustering solution enables an Alveo network that competes with InfiniBand networks in performance and latency, with no vendor lock-in. MPI integration allows for HPC developers to scale out Alveo data pipelining from the Xilinx Vitis unified software platform. 

“Scaling out Alveo compute capabilities to target HPC workloads is now easier, more efficient and more powerful than ever,” said Salil Raje, executive vice president and general manager, Data Center Group at Xilinx. “Architecturally, FPGA-based accelerators like Alveo cards provide the highest performance at the lowest cost for many compute-intensive workloads. By introducing a standards-based methodology that enables the creation of Alveo HPC clusters using a customer’s existing infrastructure and network, we’re delivering those key advantages at massive scale to any data center. This is a major leap forward for even broader adoption of Alveo and adaptive computing throughout the data center.”

CSIRO, Australia’s national research organization along with the world’s largest radio astronomy antenna array, is utilizing Alveo U55C cards for signal processing in the Square Kilometer Array radio telescope. Deploying the Alveo cards as network-attached accelerators with HBM allows for massive throughput at scale across the HPC signal processing cluster. The Alveo accelerator-based cluster allows CSIRO to tackle the massive compute task of aggregating, filtering, preparing and processing data from 131,000 antennas in real time. The 460Gbps of HBM2 bandwidth across the signal processing cluster is served by 420 Alveo U55C cards fully networked together across P4-enabled 100Gbps switches. The Alveo U55C cluster delivers processing performance with overall throughput at 15Tb/s in a compact power and cost efficient footprint. CSIRO is now completing an example Alveo reference design in order to help other radio astronomy or adjacent industries achieve the same success.

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Xilinx reports record quarter despite supply chain issues

Xilinx posted Q2 sales of $879 million, representing 3% sequential growth and 21% annual growth, despite ongoing industry-wide supply chain challenges.

Xilinx delivered another record quarter as the demand for our products remains robust, despite an unprecedented and challenging supply constrained environment,” said Victor Peng, Xilinx president and CEO. “Our stellar results were driven by strength across our diversified end markets. We continue to actively manage the supply situation with our partners, including qualifying a new supplier in a key part of our supply chain, to meet strong customer demand. In addition, we continue to execute extremely well on our roadmap as we have broadened the Versal portfolio with the Versal Edge and Versal HBM series announcements. We are working every day to improve supply for our customers.”

Some highlights:

• Data Center Group (DCG) revenue in the quarter increased 14% sequentially driven by strong demand across hyperscale cloud customers and the Fintech market
• Wired and Wireless Group (WWG) revenue was up 13% year-over-year and flat sequentially driven by continuing global 5G deployments
• Aerospace & Defense, Industrial and Test, Measurement & Emulation (AIT) revenue declined 10% sequentially, with record Industrial end market performance offset by a decline in Aerospace & Defense sales, and a modest decline in TME
• Automotive, Broadcast and Consumer (ABC) revenue in the quarter increased 13% sequentially, with record quarters in the Broadcast and Consumer end markets
• Platform transformation continues with total Adaptive SoC revenue, which includes Zynq and Versal platforms, up 13% sequentially and 83% year-over-year, and representing 28% of total revenue

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Xilinx ACAP integrates fast memory, connectivity, adaptable compute

Xilinx introduced its latest Versal HBM adaptive compute acceleration platform (ACAP), which integrate the most advanced HBM2e DRAM, providing 820GB/s of throughput and 32GB of capacity for 8X more memory bandwidth and 63% lower power than DDR5 implementations.

The Versal HBM series is architected to keep up with the higher memory needs of the most compute intensive, memory bound applications for data center, wired networking, test and measurement, and aerospace and defense.

“Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits,” said Sumit Shah, senior director, Product Management and Marketing at Xilinx. “The Versal HBM series eliminates those bottlenecks to provide our customers with a solution that delivers significantly higher performance and reduced system power, latency, form factor, and total cost of ownership for data center and network operators.”

Key features of the Versal HBM devices:

• power-optimized networking cores for high bandwidth, secure connectivity
• 5.6Tb/s of serial bandwidth with 112Gb/s PAM4 transceivers
• 2.4Tb/s of scalable Ethernet bandwidth
• 1.2Tb/s of line rate encryption throughput
• 600Gb/s of Interlaken connectivity, and 
• 1.5Tb/s of PCIe Gen5 bandwidth with built-in DMA, supporting both CCIX and CXL.

Xilinx says the new Versal HBM ACAPs deliver the network scalability and performance needed for 800G routers, switches, and security appliances. Sampling is expected in the first half of 2022. 

https://www.xilinx.com/news/press/2021/xilinx-versal-hbm-series-with-integrated-high-bandwidth-memory-tackles-big-data-compute-challenges-in-the-network-and-cloud.html

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Xilinx debuts Versal AI Edge series processors

Xilinx introduced the Versal AI Edge series processors, boasting 4X the AI performance-per-watt versus GPUs and 10X greater compute density versus previous-generation adaptive SoCs.

Xilinx is positioning the new Versal AI Edge adaptive compute acceleration platforms (ACAPs) for a range of applications including: automated driving with the highest levels of functional safety, collaborative robotics, predictive factory and healthcare systems, and multi-mission payloads for the aerospace and defense markets. The portfolio features AI Engine-ML to deliver 4X machine learning compute compared to the previous AI Engine architecture and integrates new accelerator RAM with an enhanced memory hierarchy for evolving AI algorithms. These architectural innovations deliver up to 4X AI performance-per-watt versus GPUs and lower latency resulting in far more capable devices at the edge.

"Edge computing applications require an architecture that can evolve to address new requirements and scenarios with a blend of flexible compute processing within tight thermal and latency constraints,” said Sumit Shah, senior director, Product Management and Marketing at Xilinx. “The Versal AI Edge series delivers these key attributes for a wide range of applications requiring greater intelligence, making it a critical addition to the Versal portfolio with devices that scale from intelligent edge sensors to CPU accelerators.”

The Versal AI Edge series takes the production-proven 7nm Versal architecture and miniaturizes it for AI compute at low latency, all with power efficiency as low as six watts and safety and security measures required in edge applications. As a heterogeneous platform with diverse processors, the Versal AI Edge series matches the engine to the algorithm, with Scalar Engines for embedded compute, Adaptable Engines for sensor fusion and hardware adaptability, and Intelligent Engines for AI inference that scales up to 479 (INT4) TOPS2—unmatched by ASSPs and GPUs targeting edge applications—and for advanced signal processing workloads for vision, radar, LiDAR, and software defined radio.

Sampling is available to early access customers, with shipments expected during the first half of 2022.

https://www.xilinx.com/versal-ai-edge

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Xilinx posts revenue of $851M, cites strength in wireless and data center

Citing strength in wireless and data center applications, Xilinx posted record revenues of $851 million for its fiscal fourth quarter, up 6% over the previous quarter and an increase of 13% year over year. Fiscal 2021 revenues were $3.15 billion, largely flat from the prior fiscal year.

GAAP net income for the fiscal fourth quarter was $188 million, or $0.75 per diluted share. Non-GAAP net income for the quarter was $204 million, or $0.82 per diluted share. GAAP net income for fiscal year 2021 was $647 million, or $2.62 per diluted share. Non-GAAP net income for fiscal year 2021 was $762 million, or $3.08 per diluted share.

“We are pleased with our fourth quarter results as we delivered record revenues and double-digit year-over-year growth in the midst of a challenging supply chain environment,” said Victor Peng, Xilinx president and CEO. “Xilinx saw further improvement in demand across a majority of our diversified end markets with key strength in our Wireless, Data Center and Automotive markets, the pillars of our growth strategy. Our teams have executed well and we remain focused on continuing to meet customers’ critical needs.

https://investor.xilinx.com/investor-relations

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Xilinx introduces adaptive system-on-modules for edge

Xilinx introduced its "Kria" portfolio of adaptive system-on-modules (SOMs), production-ready small form factor embedded boards for edge-based applications. 

The Xilinx SOM roadmap includes a full range of products, from cost-optimized SOMs for size and cost-constrained applications to higher performance modules that will offer developers more real-time compute capability per watt. 

The first product available in the Kria SOM portfolio, the Kria K26 SOM, specifically targets vision AI applications in smart cities and smart factories. It is built on top of the Zynq UltraScale+ MPSoC architecture, which features a quad-core Arm Cortex-A53 processor, more than 250 thousand logic cells, and a H.264/265 video codec. The SOM also features 4GB of DDR4 memory and 245 IOs, which allow it to adapt to virtually any sensor or interface. With 1.4 tera-ops of AI compute, the Kria K26 SOM enables developers to create vision AI applications offering more than 3X higher performance at lower latency and power compared to GPU-based SOMs, critical for smart vision applications like security, traffic and city cameras, retail analytics, machine vision, and vision guided robotics.

“Xilinx’s entrance into the burgeoning SOM market builds on our evolution beyond the chip-level business that began with our Alveo boards for the data center and continues with the introduction of complete board-level solutions for embedded systems,” said Kirk Saban, vice president, Product and Platform Marketing at Xilinx. “The Kria SOM portfolio expands our market reach into more edge applications and will make the power of adaptable hardware accessible to millions of software and AI developers.”

http://www.xilinx.com/kria

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Xilinx shrinks its UltraScale+ FPGAs with TSMC's InFO packaging

Xilinx expanded its UltraScale+ portfolio for markets with new applications that require ultra-compact and intelligent edge solutions. 

The company's Artix and Zynq UltraScale+ devices are now available in TSMC’s state-of-the-art InFO (Integrated Fan-Out) packaging technology, which is up to 70% smaller than traditional chip-scale packaging. 

“Demand for compact, intelligent edge applications is driving the requirement for processing and bandwidth engines to not only provide higher performance, but also new levels of compute density to enable the smallest form factor systems,” said Sumit Shah, senior director, Product Line Management and Marketing at Xilinx. “The new cost-optimized additions to our UltraScale+ portfolio are powerful enhancements that leverage the architecture and production-proven technology of Xilinx’s UltraScale+ FPGAs and MPSoCs, which collectively have been deployed in millions of systems worldwide.”

The Artix UltraScale+ family is built on its production-proven FPGA architecture and is designed for a range of applications including machine vision with advanced sensor technology, high-speed networking, and ultra-compact “8K-ready” video broadcasting. 

Artix UltraScale+ devices deliver 16 Gbps transceivers to support emerging and advanced protocols in networking, vision, and video, while also delivering the highest DSP compute in its class.

https://www.xilinx.com/news/press/2021/xilinx-expands-into-new-applications-with-cost-optimized-ultrascale-portfolio-for-ultra-compact-high-performance-edge-compute.html

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Xilinx debuts new family of Alveo SmartNICs and AI video analytics

Xilinx introduced a new family of Alveo SmartNICs, smart world AI video analytics applications, an accelerated algorithmic trading reference design for sub-microsecond trading, and a Xilinx App Store - all aimed at next gen data centers and workloads.

The Xilinx Alveo SN1000 SmartNICs, which is based on the Xilinx 16nm UltraScale+ architecture, are powered by the low-latency Xilinx XCU26 FPGA and a 16-core Arm processor. The SN1000 SmartNICs deliver dual-QSFP ports for 10/25/100Gb/s connectivity with leading small packet performance and a PCIe Gen 4 interconnect. The first model in the family is the SN1022, which is offered in a full height, half-length form factor in a 75-Watt power envelope.

The Alveo SN1000 SmartNICs deliver software-defined hardware acceleration for all function offloads. SN1000 SmartNICs directly offload CPU intensive tasks to optimize networking performance, with an open architecture that can accelerate a broad range of network functions at line rate. Programmability is provided via the company's Vitis Networking platform and industry standard, high-level programming languages such as P4, C, and C++. 

SN1000 SmartNICs provide software-defined hardware acceleration for a wide range of networking, security, and storage offloads, such as Open vSwitch and virtualization acceleration (Virtio.net). Security offloads include IPsec, kTLS and SSL/TLS and accelerated storage applications including Virtio.blk, NVMe over TCP, Ceph, and compression and crypto services.

“Data centers are transforming to increase networking bandwidth and optimize for workloads like artificial intelligence and real-time analytics,” said Salil Raje, executive vice president and general manager, Data Center Group at Xilinx. “These complex, compute-intensive and constantly-evolving workloads are pushing existing infrastructure to its limits and driving the need for fully composable, software-defined hardware accelerators that provide the adaptability to optimize today’s most demanding applications as well as the flexibility to quickly take on new workloads and protocols, and accelerate them at line rate.

In addition, Xilinx is launching an AI video analytics platform with an ecosystem of partner solutions built to accelerate the most complex and latency-sensitive AI video inferencing applications. One example use case is retail video analytics, where accelerated video processing could help identify key trends in consumer behavior.

https://www.xilinx.com/applications/data-center/network-acceleration/alveo-sn1000.html

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Fujitu leverages Xilinx for O-RAN 5G radios

Xilinx is supplying its  UltraScale+ technology to Fujitsu Limited for its O-RAN 5G radio units (O-RUs), which will be deployed in the first O-RAN-compliant 5G greenfield networks in the U.S. Fujitsu is also evaluating Xilinx RFSoC technology to further reduce cost and power consumption for additional future site deployments.

"We are proud to collaborate with Fujitsu in the development of their multi-generation 5G radio units using our industry-leading UltraScale+ solutions, which will be deployed in a major greenfield 5G network,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group at Xilinx. “As the market needs for 5G continue to evolve, Fujitsu also recognized the importance of integrating Xilinx adaptable RFSoCs to address the evolution of standards for next-generation radio deployments.”

“Our Fujitsu design team worked closely with Xilinx on our O-RAN radio units to enable greater flexibility and cost savings while also delivering greater innovation as well as new capabilities for 5G networks,” said Masaki Taniguchi, senior vice president and head of the Mobile System Business Unit at Fujitsu. 

https://www.xilinx.com/applications/wired-wireless/wireless.html

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Xilinx and Texas Instruments partner on 5G radios

Xilinx is collaborating with Texas Instruments (TI) to develop scalable and adaptable digital front-end (DFE) solutions to increase energy efficiency of lower antenna count radios. 

The collaboration will combine Xilinx's Zynq UltraScale+ MPSoC family and adaptable RF IP with the AFE7769 quad-channel RF transceiver from TI.

Xilinx's Adaptable Digital RF IP includes specialist functionality of Crest Factor Reduction (CFR) and Digital Pre-distortion (DPD). It can support a wide range of radio bandwidths and carrier configurations. Also, by being tightly integrated with the rest of the PHY processing implemented in the Zynq UltraScale+ MPSoC device, it can handle the increasingly complex signal dynamics of multi-RAT and 5G waveforms which are challenging for standalone DPD implementations. The PA technology is also evolving quickly to address these new radio requirements with broader adoption of GaN and new architectures. 

“Critical to the success of the radio platform is the efficiency and performance of the RF power amplifier (PA). Even for low-power small cell applications, the PA consumes over 50% of the power of a typical next-generation radio and is therefore key to driving the OPEX and CAPEX,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group at Xilinx. “A scalable and adaptable DFE solution that can address current and future PA efficiency needs is key for the advancement of 5G platforms.” 

“PA linearity for spectral efficiency and RF power delivery is key to achieving the performance benefits of 5G New Radio systems. Wide-bandwidth transceivers like the AFE7769 help to address higher-order PA nonlinearities and enable more efficient power delivery,” said Karthik Vasanth, vice president and business unit manager, data converters, at TI. “With this implementation, designers can address the market needs for higher instantaneous bandwidth and antenna counts to support MIMO (multiple-input, multiple-output) applications while also offering scalability to meet system cost targets.”

http://www.xilinx.com

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AMD to acquire Xilinx for $35 billion

AMD agreed to acquire Xilinx in an all-stock transaction valued at $35 billion. The acquisition price represents approximately $143 per share of Xilinx common stock.

The deal significantly expands AMD’s product portfolio, which will now cover CPUs and GPUs, with Xilinx's FPGAs, Adaptive SoCs and software expertise. The combined company's addressable market will now include industry growth segments from the data center to gaming, PCs, communications, automotive, industrial, aerospace and defense.

“Our acquisition of Xilinx marks the next leg in our journey to establish AMD as the industry’s high performance computing leader and partner of choice for the largest and most important technology companies in the world,” AMD President and CEO Dr. Lisa Su said. 

“We are excited to join the AMD family. Our shared cultures of innovation, excellence and collaboration make this an ideal combination. Together, we will lead the new era of high performance and adaptive computing,” said Victor Peng, Xilinx president and CEO. “Our leading FPGAs, Adaptive SoCs, accelerator and SmartNIC solutions enable innovation from the cloud, to the edge and end devices. We empower our customers to deploy differentiated platforms to market faster, and with optimal efficiency and performance. Joining together with AMD will help accelerate growth in our data center business and enable us to pursue a broader customer base across more markets.”

Some highlights of the combined company

• Dr. Lisa Su will lead the combined company as CEO. Xilinx President and CEO 
• Victor Peng, will join AMD as president responsible for the Xilinx business and strategic growth initiatives
• 13,000 engineers
• $2.7 billion of annual1 R&D investment
• Post-closing, current AMD stockholders will own approximately 74 percent of the combined company Immediately accretive to AMD margins, cash flow and EPS 
• Combined revenue of $11.6B 

https://www.amd.com/en/corporate/xilinx-acquisition?utm_campaign=xilinx-acquisition&utm_medium=redirect&utm_source=301

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Xilinx posts sales of $767 million - strength in data center and automotive

 Xilinx reported revenues of $767 million for the second quarter of its fiscal year 2021, up 5% sequentially but down 8% from the same period last year.

GAAP net income for the quarter was $194 million, or $0.79 per diluted share. Non-GAAP net income was $203 million, or $0.82 per diluted share.

“We are pleased with our fiscal second quarter performance, which came in above the mid-point of guidance,” said Xilinx president and CEO Victor Peng. “Our strong results were driven by another record quarter in our Data Center Group and Aerospace & Defense businesses, as well as improvement in our Automotive and Broadcast end markets. In addition, RFSoC sales ramped meaningfully with a tier-1 wireless OEM customer for 5G radio deployment in North America.

“Our strategic transformation to an adaptive platform company continues with healthy design win momentum during the quarter. Notable customer wins included a marquee SmartNIC design win with a U.S. tier-1 hyperscaler, as well as Zynq MPSoC design wins with Subaru and Continental. We also remain on track with our Versal program ramp with a leading wireless OEM later this year.”

“Xilinx business continued to strengthen in fiscal Q2, buoyed by the economic recovery and increasing demand across our broad set of end markets,” said Xilinx CFO Brice Hill. “This drove better than expected sequential revenue growth of 5% and GAAP operating income growth of 17%, resulting in $232 million of free cash flow and $93 million in capital return to stockholders with our quarterly dividend. Our financial position is strong and we remain confident as we prepare to expand the Zynq and Versal product lines and capture additional growth opportunities.”

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Xilinx samples its own telco accelerator card

Xilinx has begun sampling its own T1 Telco Accelerator Card for O-RAN distributed units (O-DUs) and virtual baseband units (vBBUs) in 5G networks. 

The card, which uses the same field-proven Xilinx silicon and IP already being deployed in 5G networks, comes in a multi-function PCIe form factor card which performs both O-RAN fronthaul protocols and layer 1 offload. The card provides advanced workload offload capabilities, enabling a dramatic reduction in the number of CPU cores required in a system. The T1 card also enables the O-DU to deliver greater 5G performance and services while reducing overall system power consumption and cost compared to competitive offerings.

The T1 card is a small form factor, single-slot card that can be plugged into standard x86 or non-x86 servers to achieve the real-time protocol processing performance required for 5G virtualized O-DU platforms. In addition, it offloads line-rate and compute-intensive functions including: channel encoding/decoding using hardened LDPC and Turbo codecs, rate matching/de-matching, HARQ buffer management, and more, freeing the processor cores for running other services - the true promise of virtualization. The T1 card simplifies 5G deployments by offering a turnkey solution through ecosystem partners that includes both O-RAN fronthaul and 5G NR layer 1 reference designs, as well as pre-validated software to enable operators, system integrators, and OEMs to get to market quickly.

Xilinx says the offloading of critical channel coding functions from the CPU to the T1 card delivers up to 45x encoding and 23x decoding throughput improvement relative to the same server without acceleration. The T1 card enables the use of fewer CPU cores, driving down system cost and overall power consumption. Additionally, for O-RAN fronthaul termination, it can process multiple sectors of 5G NR 4TRX at 100 MHz OBW with its 50 Gbps of optical ports. The Fronthaul and L1 bandwidths are matched for optimal scalability; the more towers you want, the more cards you add to the server.

“The trend toward network virtualization and O-RAN has given us an opportunity with the Xilinx T1 Telco Accelerator Card to drive the next steps of disaggregation of standard networks, enabling our expansion into every corner of the 5G market,” said Dan Mansur, vice president of marketing, Wired and Wireless Group, Xilinx. “Working closely with our ecosystem partners, Xilinx hardware, IP and software are leading the innovation and realization of 5G O-RAN networks.”

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Ribbon announces 5G slicing based on Xilinx

Ribbon Communications is developing a 5G hybrid slicing solution in collaboration with Xilinx. Further details are expected later this month.

"Today's announcement highlights our leadership and innovation in packet optical networking," said Sigal Barda, Ribbon's VP of Product and Head of 5G Portfolio. "Our hybrid slicing capabilities enable operators to simultaneously deliver tomorrow's resource-intensive and low latency 5G services while gaining operational efficiencies from their networks, thereby maximizing the value of their infrastructure investment."

"We value our relationship with Ribbon and the advances we've made in the packet optical networking space together," said Safy Fishov, Vice President of Sales for North America and Europe, Wired and Wireless Group at Xilinx. "Thanks to our leading Virtex UltraScale+ technology, design services, and FLEX-E solution, Ribbon is helping to move the industry forward, offering an elegant hybrid slicing solution to support new 5G use and business cases including network sharing, private networks slices, and new mobile-based services online for gaming and eHealth."\

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Xilinx sees strength in data center product and some order acceleration

Xilinx reported revenues of $727 million for the first quarter of its fiscal year 2021,  exceeding initial guidance and in-line with revised guidance. GAAP net income for the quarter was $94 million, or $0.38 per diluted share. Non-GAAP net income was $160 million, or $0.65 per diluted share.

The company noted record Data Center Group (DCG) revenue, with 10% sequential and 104% annual growth. Wireless Group (WWG) revenue increased 27% sequentially.

“Our fiscal Q1 revenue was well above the initial guidance despite ongoing business challenges from COVID-19 and global trade issues,” said Xilinx president and CEO Victor Peng. “Results were driven by strength in the Data Center Group (DCG), Wired and Wireless Group (WWG), and the Industrials market, offsetting expected headwinds in consumer-oriented end markets, including Automotive and Broadcast. The outperformance was due to a combination of strength in multiple end markets, as well as some order acceleration driven by recent additional U.S. government trade restrictions on sales of certain Xilinx products to some customers based, or with operations, in China.”

http://investor.xilinx.com/

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Xilinx raises its revenue guidance

Xilinx raised the range of its prior guidance for its first quarter of fiscal 2021 ended June 27, 2020. The new expectations are as follows:

“While we have seen some COVID-19 related impacts during the June quarter, our business has generally performed well overall, with stronger than expected revenues in our Wired and Wireless Group and Data Center Group more than offsetting weaker than expected revenues in our consumer-oriented end markets, including automotive, broadcast, and consumer. A portion of the revenue strength in the quarter was due to customers accelerating orders following recent changes to the U.S. government restrictions on sales of certain of our products to international customers,” said Victor Peng, Xilinx’s President and Chief Executive Officer.

“Given our preliminary assessment of the expected financial results in the June quarter, we are raising the midpoint for revenue and narrowing our overall guidance ranges. Furthermore, we are updating our expected tax rate for the June quarter to include the prior and current year potential impacts of the Altera Corp. v. Commissioner tax case, a third-party legal proceeding concerning related-party R&D cost sharing arrangements and stock-based compensation. The potential impact for prior years is approximately $57 million while the impact to the fiscal 2021 expected tax rate is an additional 1%-2%.”

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Xilinx spins 20-nm, radiation-tolerant, space-grade FPGAs

Xilinx introduced a 20-nanometer (nm) space-grade FPGA, offering full radiation tolerance and ultra-high throughput and bandwidth performance for satellite and space applications.

The new 20nm Radiation Tolerant (RT) Kintex UltraScale XQRKU060 FPGA provides true unlimited on-orbit reconfiguration, over a 10x increase in digital signal processing (DSP) performance – ideal for payload applications – and full radiation tolerance across all orbits.

The XQRKU060 offers rich DSP capabilities optimized for dense power-efficient compute. It is equipped with 2,760 UltraScale DSP slices and provides up to 1.6 TeraMACs of signal processing compute, more than a 10X increase compared to the prior generation, as well as dramatic efficiency gains for floating point computations. The increased compute capability in space is paired with massive I/O bandwidth from 32 high-speed transceivers (SerDes) that can run up to 12.5Gbps to deliver 400Gbps aggregate bandwidth.

The XQRKU060 also features robust 40x40mm ceramic packaging capable of withstanding vibrations and handling during launch as well as radiation effects in harsh orbit environments. The architecture features an innovative design for single event effects (SEE) mitigation thereby meeting the industry requirements for all orbits, including low earth orbit (LEO), medium earth orbit (MEO), geosynchronous orbit (GEO), and deep space missions.

“With our extensive history in developing leading-edge, radiation tolerant technology and deploying this in reliable space-grade solutions, Xilinx continues its lead with the launch of the world’s most advanced process node for space,” said Minal Sawant, space systems architect, Aerospace and Defense Vertical Marketing, at Xilinx. “The 20nm RT Kintex UltraScale FPGA is breaking industry standards and setting a new benchmark for meeting the high compute requirements of high bandwidth payloads, space exploration and research missions.”

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Xilinx posts quarterly revenue of $756 million

Xilinx announced revenues of $3.16 billion for fiscal year 2020, up 3% from the prior fiscal year. Revenues were $756 million for the fourth quarter of fiscal year 2020, up 5% from the prior quarter and down 9% year over year.

GAAP net income for fiscal year 2020 was $793 million, or $3.11 per diluted share. Non-GAAP net income for fiscal year 2020 was $853 million, or $3.35 per diluted share. GAAP net income for the March quarter was $162 million, or $0.65 per diluted share. Non-GAAP net income for the March quarter was $193 million, or $0.78 per diluted share.

“Despite our fiscal 2020 being uniquely challenging, particularly related to the US trade-related restrictions with Huawei as well as some COVID-19 impact during our Q4, we were able to deliver another record year with revenue of $3.16 billion, a 3% increase over fiscal 2019,” said Xilinx president and CEO Victor Peng. “The strength and diversity of our business were reflected in the results of our fiscal fourth quarter with strong sequential growth in both revenue and profitability.”

“There remains a high degree of uncertainty in the global business environment given the impact of COVID-19 which creates challenges with visibility beyond the near term. Therefore, we believe it is prudent to provide only quarterly guidance at this time. We will continue to closely monitor business conditions. Lastly, I want to thank our employees for their continued focus and commitment in these challenging times.”

The Xilinx Board of Directors declared a quarterly cash dividend of $0.38 per outstanding share of common stock payable on June 3, 2020 to all stockholders of record at the close of business on May 13, 2020. The declared dividend represents a 2.7% increase over the prior quarter’s dividend and reflects Xilinx’s commitment to growing the dividend.

http://www.xilinx.com

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