SiFive intros RISC-V processors for automobiles

SiFive introduced three RISC-V processors for automotive manufacturers and their suppliers.

The processors target current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification, as the market transitions to zonal architectures and manufacturers require the energy efficiency, simplicity, security, and software flexibility that RISC-V offers. 

“SiFive is combining the best RISC-V benefits in the only end-to-end portfolio designed to meet automotive needs today and long into the future,” said Patrick Little, CEO and Chairman, SiFive. “We are seeing widespread interest in our new RISC-V automotive solutions and are working closely with several leading semiconductor companies and top-tier suppliers, who are turning to the flexibility of our highest performance cores in areas like safety-critical compute applications. Customers are now able to take advantage of our latest, most powerful cores to bring exciting innovations to consumers.”

“Renesas has been closely collaborating with SiFive to bring the strong benefits of RISC-V to many of our products,” said Takeshi Kataoka, Senior Vice President and General Manager of the Automotive Solution Business Unit at Renesas. “RISC-V continues to gain momentum around the world, and we plan to leverage SiFive’s portfolio of automotive RISC-V products in our future automotive SoC solutions to meet the exacting demands of these global customers. Partnering with an innovation leader like SiFive is a logical step that allows us to fuel our growth and meet our customer’s evolving requirements.”

https://www.SiFive.com

SiFive raises $175 million in Series F funding for RISC-V

Monday, March 21, 2022  RISC-V, SiFive, Silicon, Start-Ups  

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions, raised $175 million in a Series F financing round, valuing the company at over $2.5 billion. SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. The Series F round was led by Coatue Management, a global...

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Alphawave IP to acquire OpenFive Business Unit from SiFive for $210m

Monday, March 14, 2022  Mergers And Acquisitions, SiFive  

Alphawave IP Group plc agreed to acquire the entire OpenFive business unit from SiFive for US$210 million in cash.SiFive is the founder and leader of RISC-V computing based in San Mateo, California. OpenFive, a SiFive business unit, has a high-speed connectivity system-on-chip (SoC) IP portfolio and a proven team based in India and Silicon Valley that has been delivering custom silicon solutions for over 15 years.  The acquisition significantly...

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SiFive raises $175 million in Series F funding for RISC-V

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions, raised $175 million in a Series F financing round, valuing the company at over $2.5 billion. 

SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. 

The Series F round was led by Coatue Management, a global technology investment firm. Coatue joins existing investors AMD (through Xilinx Ventures), Ibex Investors, Intel Capital, Osage University Partners, Prosperity7 ventures, Qualcomm Ventures, Samsung Ventures, SK hynix, Spark Capital, Sutter Hill Ventures, and Western Digital Capital.

“The market has spoken and made it abundantly clear that RISC-V computing will be competing for the heart of all future computing platforms. As the founder and market leader of RISC-V computing it’s our role to lead this ecosystem forward and offer customers advanced computing alternative to Arm and others,” said Patrick Little, CEO and Chairman, SiFive. “This valuation is a validation of our strategy, our incredible team, and our singular focus on building the leading portfolio of high-performance RISC-V compute products in the market. Our customers are signaling strong demand for SiFive to deliver the highest level of performance as quickly as possible.”

“We continue to be impressed by SiFive’s growth and challenge to proprietary legacy architecture IP providers,” said Jaimin Rangwalla, Senior Managing Director at Coatue Management. “SiFive’s accomplishments in high-performance RISC-V IP enables future computing platforms to be built on an open, industry-wide base, allowing technology companies to design differentiated products for their target markets. We are proud to partner with and support the team as they create an exciting future for the company.”

“Intel believes in enabling a multi-ISA strategy, including RISC-V as the open compute base for future platforms,” said Bob Brennan, VP & GM, Customer Solutions Engineering, Intel Foundry Services. “Our IFS investment in RISC-V includes partnering with RISC-V leader SiFive to build the Horse Creek developer platform that will be broadly available in late 2022, based on Intel 4 process technology.”

https://www.sifive.com

• To date, SiFive has raised over $350 million.

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EdgeQ samples its RISC-V 5G base station-on-a-Chip

EdgeQ, a start-up based in Santa Clara, California, is now sampling its RISC-V based, 5G Base Station-on-a-Chip to customers developing enterprise-grade 5G access points, Open-Radio Access Network (O-RAN) based Radio Unit (RU) and Distributed Unit (DU).

The EdgeQ platform combines highly integrated silicon with up to 50 RISC-V cores and 5G PHY software for processing all key functionalities and critical algorithms of the radio access network such as beamforming, channel estimation, massive MIMO and interference cancellation. The design is programmable and provides an open framework for L2/L3 software partners. 

EdgeQ, which has been developing its platform for the past three years, said traditional merchant silicon vendors offer the PHY as a reference software, placing the development burden on customers to invest years of effort to operationalize into production. By abstracting this friction with a total platform solution including a production-readied 5G PHY software, EdgeQ frees customers from the substantial investments, resources and time typically associated with productizing the 4G/5G PHY stack.

“Since day one, EdgeQ has been relentless about redefining the consumption and deployment model of 5G with its RISC-V based open architecture that converges connectivity, networking, and compute. How we elegantly club the hardware, the deployable RAN software, and an innovative chipset-as-a-service business model all together is what crystallizes the vision in a disruptively compelling way,” said Vinay Ravuri, CEO and Founder, EdgeQ. “Our sampling announcement today signifies that all this is a market reality.”

http://www.edgeq.io

EdgeQ pursues a feature subscription model for 5G basestation chip

Wednesday, June 16, 2021  EdgeQ  

EdgeQ, a start-up offering a 5G systems-on-a-chip, introduced a 5G chipset-as-a-service model in which customers can scale 5G and AI features as a function of subscription payments.  The service-oriented model would enable customers to scale from nominal to advanced 5G features such as ultra-reliable low latency communications, geo-location services, massive MIMO, fine-grained network slicing, as well as extending compatibility to other legacy wireless protocols. 

The company says its new service model is the very first in the chip industry to scale price, performance, and features as a function of need and use.  The potential is to elevate 5G Open Radio Access network (O-RAN) to an even more configurable, elastic, open wireless infrastructure. Enterprise network, telco, and cloud providers might also use the EdgeQ model to virtualize network resources.

“Our vision at EdgeQ has always been about implementing 5G in a format that is accessible, consumable, and intuitive for our customers. EdgeQ is not only the first company to converge both 5G and AI on a single chip for wireless infrastructure, but we are also able to make those capabilities available in a SaaS model.  This fundamentally reduces the initial capex investment required for 5G, thereby removing both technical and economic barriers of 5G adaptation at greenfield enterprises,” said Vinay Ravuri, CEO and Founder, EdgeQ. “This pay-as-you-go model ensures that the evolving demands of the market can leverage the full fluidity and elasticity of EdgeQ’s 5G-as-a-Service product.”

https://edgeq.io/

Video: New Silicon and Open Software Driving a New Ecosystem

There’s a plethora of interest in the 5G space from operators to enterprises and cloud service providers. In this video, Vinay Ravuri, CEO and Founder of EdgeQ, talks about how box makers are transforming with the emerging 5G market and how open software is driving a new set of markets.

https://youtu.be/KyRgSlZBpQQ

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SiFive licenses its RISC-V core IP to Renesas

Renesas Electronics and SiFive agreed to jointly develop next-generation, high-end RISC-V solutions for automotive applications. The partnership will also include SiFive licensing the use of their RISC-V core IP portfolio to Renesas.

Renesas provides automotive solutions including ADAS, Autonomous Driving (AD), Electric Vehicles (EV), and Connected Gateway (CoGW) to customers all over the world.

The SiFive Intelligence platform, based on SiFive RISC-V Vector processors with AI ISA extensions, features a differentiated software toolchain to enable the development of scalable solutions for AI and ML applications. SiFive RISC-V processors are pre-integrated with advanced trace, debug, and security solutions compatible with industry tools to simplify heterogeneous integration and migration. 

“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.”

“We are excited to collaborate with Renesas to develop next-generation automotive solutions powered by the SiFive Intelligence platform,” said Patrick Little, Chairman and CEO, SiFive. “Our roadmap of advanced, high-performance RISC-V processor cores and AI accelerators will deliver significant core performance increases with the capabilities needed to meet Automotive application requirements, along with enhanced AI capabilities to power scalable, workload-accelerated solutions.”

http://www.sifive.com

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SiFive raises $61 million for RISC-V

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions,  raised $61 million in a Series E round.

SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. Recently, SiFive announced the SiFive 20G1 update for SiFive Core IP, enabling significant enhancements for performance, power, area, and features, with pre-integrated SiFive Shield, for whole SoC security, and SiFive Insight advanced trace and debug capabilities.

The latest funding round was led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures LLC, Intel Capital, Osage University Partners, and Spark Capital.

“Global demand for storage and memory in the data center is increasing as AI-powered business intelligence and data processing growth continues”, said Youjong Kang, VP of Growth Strategy, SK hynix. “SiFive is well-positioned to grow with opportunities created from data center, enterprise, storage and networking requirements for workload-focused processor IP.”

http://www.sifive.com

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Andes' RISC-V processor qualified for Amazon FreeRTOS

Andes Technology's Corvette-F1 N25 platform is one of the first RISC-V platforms qualified for Amazon FreeRTOS.

Amazon FreeRTOS is an open source operating system for microcontrollers from Amazon Web Services (AWS) designed for small, low-power edge devices.

“IoT, and AIoT, will be a big addressable market for RISC-V CPU,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “By leveraging the advantages of Amazon FreeRTOS and Andes RISC-V platform, we can provide developers using Amazon FreeRTOS additional development platform choices and strengthen the Andes RISC-V IoT solutions for our customers.”

Andes' Corvette-F1 N25 platform is a FPGA-based Arduino-compatible evaluation platform. It comes with a 32-bit RISC-V AndesCore N25 running at 60MHz, 4MB Flash, 256KB instruction SRAM and 128KB data SRAM, and AndeShape AE250 Platform IP with rich peripherals such as GPIO, I2C, PWM, SPI, and UART. It also contains an on-board wireless module supporting IEEE 802.11 b/g/n.

http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-n25/

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RISC-V base instruction set architecture approved

The RISC-V Foundation has ratified the RISC-V base instruction set architecture (ISA) and privileged architecture specifications.

Software that’s coded to this specification will continue to work on RISC-V processors in perpetuity, even as the architecture evolves through the development of new extensions.

“RISC-V was designed with a simple fixed base ISA and modular fixed standard extensions to help prevent fragmentation while also supporting customization,” said Krste Asanović, chairman of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem has already demonstrated a large degree of interoperability among various implementations. Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever.”

Privilege levels are used to provide protection between different components of the software stack, and attempts to perform operations not permitted by the current privilege mode will cause an exception to be raised. The RISC-V privileged architecture covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices. Each privilege level has a core set of privileged ISA extensions with optional extensions and variants, including the machine ISA, supervisor ISA and hypervisor ISA.

“The RISC-V privileged architecture serves as a contract between RISC-V hardware and software such as Linux and FreeBSD. Ratifying these standards is a milestone for RISC-V,” said Andrew Waterman, chair of the RISC-V Privileged Architecture Task Group. “Operating system developers and hardware vendors can build to these specs with confidence that their work will be compatible.”

The RISC-V Foundation has seen significant growth over the past few years with more than 275 organizations, individuals, and universities from 28 countries and six continents around the world. The RISC-V ISA has already witnessed rising commercial adoption and implementations across a variety of industries.

https://riscv.org/specifications/privileged-isa/

• The RISC-V Foundation, which was founded in 2015, now comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation.

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Calista Redmond appointed CEO of RISC-V Foundation

Calista Redmond has been appointed Chief Executive Officer (CEO) of the RISC-V Foundation, which promotes the adoption and implementation of the free and open RISC-V instruction set architecture (ISA).

Redmond brings more than 20 years of senior-level management and alliance experience, including as Vice President of IBM Z Ecosystem, where she was instrumental in growing the IBM Z Ecosystem. During her 12 years at IBM, she led strategic relationships with chip, hardware, and software providers, system integrators, business partners, clients, and developers, as well as fostered broader industry visibility and engagement.  Redmond was instrumental in the strategic formation of OpenPOWER as the IBM Director of OpenPOWER Global Alliances as well as elected President of the OpenPOWER Foundation in 2016.

“I’ve always understood the potential short- and long-term impact of the RISC-V license-free ISA on the open source community. Having spent a lot of my career working in the open source ecosystem, I’m excited to help RISC-V grow and deliver on  the Foundation’s mission of paving the way for the next 50 years of computing design and innovation,” said Redmond, CEO of the RISC-V Foundation. “From its inception in 2015 until now, the RISC-V Foundation has grown tremendously. I’m ready to leverage that momentum to expand the already impressive RISC-V ecosystem.”

The RISC-V Foundation, which was founded in 2015, now comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation.

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