Showing posts with label CXL. Show all posts
Showing posts with label CXL. Show all posts

Thursday, November 17, 2022

Astera Labs raises $150M for its CXL platform

Astera Labs, a start-up based in Santa Clara, California, raised $150 million in Series-D funding with a $3.15B valuation for its data and memory connectivity solutions based on Compute Express Link (CXL), PCIe, and Ethernet technologies. 

Fidelity led the funding round and was joined by other existing investors, including Atreides Management, Intel Capital, and Sutter Hill Ventures.

“Astera Labs continues to surpass every milestone for a technology start-up, and we are now deep into the next stage of evolution for our company as we accelerate growth,” said Jitendra Mohan, CEO, Astera Labs. “This latest funding round is a testament that we are not only invested in the right growth markets such as Cloud, Artificial Intelligence/Machine Learning, and Hyperscale infrastructure, but that we are also able to consistently execute and deliver breakthrough connectivity products that are critical to our customers and partners.”

In its Series-D funding round led by Fidelity Management and Research, Astera Labs 

“Astera Labs has successfully executed on its vision to be the Cloud industry’s trusted connectivity partner,” said Stefan Dyckerhoff, Managing Director at Sutter Hills Ventures, and Board Member of Astera Labs. “I’m extremely impressed by the company’s ability to assert itself as the leader in the Cloud infrastructure market that increasingly demands purpose-built connectivity solutions to remove performance bottlenecks.”

In addition, Astera Labs has elected to its board of directors Dr. Alexis Black Bjorlin, VP of Infrastructure, Meta, and Michael Hurlston, President, and CEO, Synaptics Incorporated.

Alexis Black Bjorlin leads the Infrastructure Hardware team at Meta to drive technology innovation. She brings to Astera Labs expertise in hardware, semiconductors, and systems, and in scaling operations. Prior to Meta, Bjorlin held senior executive positions as SVP and GM of Broadcom’s optical systems division and as Corporate VP of the Data Center Group and GM of the Connectivity Group at Intel.

Michael Hurlston has served as President and CEO of Synaptics since 2019. Previously, he served as CEO and board member of Finisar Corporation and as SVP and GM of the Mobile Connectivity Products/Wireless Communications and Connectivity Division as well as other leadership positions at Broadcom. Astera Labs will be able to tap into Hurlston’s extensive semiconductor technology and business expertise.

“I am pleased to welcome these visionary leaders to the Astera Labs’ Board of Directors,” said Manuel Alba, Chairman of the Board, Astera Labs. “Their passion for transformative technology, combined with expertise in semiconductors, cloud, and the data center industry, will add valued insights to the board and help Astera Labs continue to scale.”

https://www.asteralabs.com/news/astera-labs-accelerates-company-growth-with-series-d-funding-and-expanded-board-of-directors/

OCP: Introducing CXL Memory Pooling

https://youtu.be/3TsYgWaKGuUAstera Labs has demonstrated the industry's first CXL memory pooling solution to reduce memory stranding, optimize memory utilization and reduce TCO for cloud servers. The demo shows how memory pooling can be deployed today with Leo and CXL 1.1-capable 4th Gen Intel Xeon processors.Presented by Ahmad Danesh, Sr. Director,  Product Management, Astera Labs.New CXL 3.0 spec doubles the data rate to 64GTsTuesday,...

Video: 800G over Copper at 3m

 What's hot at DesignCon22?  Sanjay Gajendra talks about AsteraLabs' Smart Cable Modules for 100G/Lane Ethernet Switch-to-Switch and Switch-to-Server interconnects.https://youtu.be/ndTKntb_0_AAstera Labs' module enables copper-based Smart Electrical Cables at up to 800 GbEMonday, November 15, 2021  AEC, Astera, Data Centers  Astera Labs introduced its new Taurus Smart Cable Module portfolio to overcome performance...


Monday, October 24, 2022

OCP: Introducing CXL Memory Pooling


https://youtu.be/3TsYgWaKGuU

Astera Labs has demonstrated the industry's first CXL memory pooling solution to reduce memory stranding, optimize memory utilization and reduce TCO for cloud servers. 

The demo shows how memory pooling can be deployed today with Leo and CXL 1.1-capable 4th Gen Intel Xeon processors.

Presented by Ahmad Danesh, Sr. Director,  Product Management, Astera Labs.

New CXL 3.0 spec doubles the data rate to 64GTs

The CXL Consortium announced the release of the CXL 3.0 specification, doubling the data rate to 64GTs compared to the 2.0 generation.The idea with CXL is to maintain memory coherency between the CPU memory space and memory on attached devices, allowing resource sharing. “Modern datacenters require heterogenous and composable architectures to support compute intensive workloads for applications such as Artificial Intelligence and Machine Learning...

Marvell to acquire Tanzanite for Compute Express Link (CXL)

Marvell agreed to acquire privately-held Tanzanite Silicon Solutions, a start-up based in Milpitas, California that is developing advanced Compute Express Link (CXL) technologies. Terms of the all-cash transaction were not disclosed. Marvell said the future cloud data center will be built on fully disaggregated architecture utilizing CXL technology, requiring greater high-speed interconnectivity than ever combined with optimized compute, networking,...

Tuesday, August 2, 2022

New CXL 3.0 spec doubles the data rate to 64GTs

The CXL Consortium announced the release of the CXL 3.0 specification, doubling the data rate to 64GTs compared to the 2.0 generation.

The idea with CXL is to maintain memory coherency between the CPU memory space and memory on attached devices, allowing resource sharing.


“Modern datacenters require heterogenous and composable architectures to support compute intensive workloads for applications such as Artificial Intelligence and Machine Learning – and we continue to evolve CXL technology to meet industry requirements,” said Siamak Tavallaei, president, CXL Consortium. “Developed by our dedicated technical workgroup members, the CXL 3.0 specification will enable new usage models in composable disaggregated infrastructure.”

Highlights of the CXL 3.0 specification:

  • Fabric capabilities
  • Multi-headed and Fabric Attached Devices o Enhanced Fabric Management
  • Composable disaggregated infrastructure
  • Better scalability and improved resource utilization o Enhanced memory pooling
  • Multi-level switching
  • New enhanced coherency capabilities o Improved software capabilities
  • Doubles the bandwidth to 64GTs
  • Zero added latency over CXL 2.0
  • Full backward compatibility with CXL 2.0, CXL 1.1, and CXL 1.0

Board members of the CXL Consortium included Alibaba, AMD, Arm, Cisco, Dell, Google, HPE, Huawei, IBM, Intel, Meta, Micron, Microsoft, Nvidia, and Samsung. 

https://www.computeexpresslink.org/download-the-specification


Marvell to acquire Tanzanite for Compute Express Link (CXL)

Marvell agreed to acquire privately-held Tanzanite Silicon Solutions, a start-up based in Milpitas, California that is developing advanced Compute Express Link (CXL) technologies. Terms of the all-cash transaction were not disclosed. Marvell said the future cloud data center will be built on fully disaggregated architecture utilizing CXL technology, requiring greater high-speed interconnectivity than ever combined with optimized compute, networking,...

Rambus to acquire Hardent for semiconductor design team

Rambus agreed to acquire Hardent, a professional services company specializing in electronic product design and engineering. The company, which is based in Montreal, has 20 years of semiconductor experience in silicon design, verification, compression, and Error Correction Code (ECC). Financial terms were not disclosed.Rambus says the acquisition augments its team of engineers at Rambus and accelerates the development of CXL processing solutions...


Tuesday, November 10, 2020

CXL Consortium releases 2.0 spec for CPU-to-device interconnect

The CXL Consortium, which was formed in 2019 to develop an open industry standard group for high-speed CPU interconnect, announced the release of the CXL 2.0 specification. 

CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory – all while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.

Key Highlights of the CXL 2.0 Specification:

  • Adds support for switching to enable device fan-out, memory scaling, expansion and the migration of resources.
  • Includes memory pooling support to maximize memory utilization, limiting or eliminating the need to overprovision memory.
  • Introduces standardized fabric manager specification for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.
  • Provides standardized management of the persistent memory interface and enables simultaneous operation alongside DDR, freeing up DDR for other uses.
  • Introduces managed hot-plug support to take a CXL device online or offline from the system.
  • Adds link-level Integrity and Data Encryption (CXL IDE) to provide confidentiality, integrity and replay protection for data transiting the CXL link.
  • Supports a wide variety of industry interconnect form factors and standardized management interfaces to ease implementation.
  • Includes Compliance and Interoperability specifications and in-system testing to enable a robust and interoperable multi-vendor ecosystem.

Compute Express Link (CXL) promises high-speed CPU interconnect

Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel and Microsoft have teamed up to form Compute Express Link (CXL), an open industry standard group for high-speed CPU interconnect.


CXL will maintain memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. The technology is built upon PCI Express (PCIe) infrastructure, leveraging the PCIe 5.0 physical and electrical interface to provide advanced protocol in three key areas:

  • I/O Protocol 
  • Memory Protocol, initially allowing a host to share memory with an accelerator
  • Coherency Interface
The group has completed work on a CXL Specification 1.0 for interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions.

https://www.computeexpresslink.org/